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| motorola.com/semiconductors m68hc08 microcontrollers mc68hc908jl3e/d r e v . 2, 1 2 /2 0 02 mc68hc908jl3e mc68hc908jk3e te c h n i c a l d a t a mc68hc908jk1e mc68hrc908jl3e mc68hrc908jk3e mc68hrc908jk1e mc68HLC908JL3E mc68hlc908jk3e mc68hlc908jk1e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola 3 mc68hc908jl3e/jk3e/jk1e mc68hrc908jl3e/jk3e/jk1e mc68HLC908JL3E/jk3e/jk1e technical data motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola, inc. is an equal opportunity/affirmative action employer. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. ? motorola, inc., 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . revision history technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 4 motorola to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://motorola.com/semiconductors the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. revision history date revision level description page number(s) dec 2002 2 added appendix a for low-volt devices. 217?224 updated monitor mode circuit ( figure 9-1 ) and monitor mode entry requirements and options ( table 9-1 ) in monitor rom section. 109, 110 may 2002 1 first general release. ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola list of sections 5 technical data ? mc68h(r)c908jl3e/jk3e/jk1e list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 23 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 31 section 3. random-access memory (ram) . . . . . . . . . . 41 section 4. flash memory (flash) . . . . . . . . . . . . . . . . 43 section 5. configuration register (config) . . . . . . . . . 53 section 6. central processor unit (cpu) . . . . . . . . . . . . 57 section 7. system integration module (sim) . . . . . . . . . 77 section 8. oscillator (osc) . . . . . . . . . . . . . . . . . . . . . . 101 section 9. monitor rom (mon) . . . . . . . . . . . . . . . . . . . 107 section 10. timer interface module (tim) . . . . . . . . . . . 121 section 11. analog-to-digital converter (adc) . . . . . . 143 section 12. input/output (i/o) ports . . . . . . . . . . . . . . . 153 section 13. external interrupt (irq) . . . . . . . . . . . . . . . 165 section 14. keyboard interrupt module (kbi). . . . . . . . 171 section 15. computer operating properly (cop) . . . . 179 section 16. low voltage inhibit (lvi) . . . . . . . . . . . . . . 185 section 17. break module (break) . . . . . . . . . . . . . . . 189 section 18. electrical specifications. . . . . . . . . . . . . . . 197 section 19. mechanical specifications . . . . . . . . . . . . . 209 section 20. ordering information . . . . . . . . . . . . . . . . . 213 appendix a. mc68HLC908JL3E/jk3e/jk1e. . . . . . . . . 217 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola table of contents 7 technical data ? mc68h(r)c908jl3e/jk3e/jk1e table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 4. flash memory (flash) 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 8 table of contents motorola 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.5 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.9 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . 50 section 5. configuration register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 section 6. central processor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola table of contents 9 section 7. system integration module (sim) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 81 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . .81 7.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . . 83 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.4.2.2 computer operating properly (cop) reset. . . . . . . . . . . 85 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.2.5 lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . 86 7.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . . 86 7.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . .87 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.6.2 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.2.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . .94 7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 10 table of contents motorola 7.8.1 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . .97 7.8.2 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . 98 7.8.3 break flag control register (bfcr) . . . . . . . . . . . . . . . . . 100 section 8. oscillator (osc) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3 x-tal oscillator (mc68hc908jl3e/jk3e/jk1e). . . . . . . . . . . 102 8.4 rc oscillator (mc68hrc908jl3e/jk3e/jk1e) . . . . . . . . . . 103 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 104 8.5.2 crystal amplifier output pin (osc2/pta6/rcclk). . . . . . 104 8.5.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 104 8.5.4 x-tal oscillator clock (xtalclk). . . . . . . . . . . . . . . . . . . . 104 8.5.5 rc oscillator clock (rcclk). . . . . . . . . . . . . . . . . . . . . . . 105 8.5.6 oscillator out 2 (2oscout) . . . . . . . . . . . . . . . . . . . . . . . 105 8.5.7 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.7 oscillator during break mode. . . . . . . . . . . . . . . . . . . . . . . . . 106 section 9. monitor rom (mon) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.4.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.4.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.4.4 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.4.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola table of contents 11 9.4.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 section 10. timer interface module (tim) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 126 10.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . .127 10.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . .127 10.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 128 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . .129 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . .134 10.10.2 tim counter registers (tcnth:tcntl) . . . . . . . . . . . . . . 136 10.10.3 tim counter modulo registers (tmodh:tmodl) . . . . . . 137 10.10.4 tim channel status and control registers (tsc0:tsc1) .138 10.10.5 tim channel registers (tch0h/l:tch1h/l) . . . . . . . . . . 142 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 12 table of contents motorola section 11. analog-to-digital converter (adc) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7.1 adc voltage in (adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . . 148 11.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 151 section 12. input/output (i/o) ports 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 157 12.3.3 port a input pull-up enable register (ptapue) . . . . . . . . 158 12.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 160 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola table of contents 13 12.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.5.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 162 12.5.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 163 12.5.3 port d control register (pdcr). . . . . . . . . . . . . . . . . . . . . 164 section 13. external interrupt (irq) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.4.1 irq1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . .169 13.6 irq status and control register (intscr) . . . . . . . . . . . . . . 169 section 14. keyboard interrupt module (kbi) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.4.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.4.2 keyboard status and control register. . . . . . . . . . . . . . . . 175 14.4.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 176 14.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.6 keyboard module during break interrupts . . . . . . . . . . . . . . .177 section 15. computer operating properly (cop) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 14 table of contents motorola 15.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.1 2oscout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.5 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.4.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 15.4.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 15.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 15.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . .184 section 16. low voltage inhibit (lvi) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 16.5 lvi control register (config2/config1) . . . . . . . . . . . . . . 186 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 section 17. break module (break) 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola table of contents 15 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.4.1 flag protection during break interrupts . . . . . . . . . . . . . . .192 17.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 192 17.4.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . 192 17.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 192 17.5 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 17.5.1 break status and control register (brkscr) . . . . . . . . . 193 17.5.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . .194 17.5.3 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 17.5.4 break flag control register (bfcr) . . . . . . . . . . . . . . . . . 196 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 section 18. electrical specifications 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 18.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .198 18.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 199 18.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 18.6 5v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 200 18.7 5v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.8 5v oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 202 18.9 3v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 203 18.10 3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 18.11 3v oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.12 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 18.13 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.14 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 16 table of contents motorola section 19. mechanical specifications 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.3 20-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.4 20-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.5 28-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.6 28-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.7 48-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 section 20. ordering information 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 20.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 appendix a. mc68HLC908JL3E/jk3e/jk1e a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 a.3 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a.4 low-voltage inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a.5 oscillator options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a.6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a.6.1 functional operating range . . . . . . . . . . . . . . . . . . . . . . . 218 a.6.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 219 a.6.3 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 a.6.4 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .220 a.6.5 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 a.6.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 a.7 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola list of figures 17 technical data ? mc68h(r)c908jl3e/jk3e/jk1e list of figures figure title page 1-1 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1-2 28-pin pdip/soic pin assignment . . . . . . . . . . . . . . . . . . . . . 27 1-3 20-pin pdip/soic pin assignment . . . . . . . . . . . . . . . . . . . . . 27 1-4 48-pin lqfp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . .28 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .34 4-1 flash i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . 44 4-2 flash control register (flcr) . . . . . . . . . . . . . . . . . . . . . . . 45 4-3 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 49 4-4 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 50 5-1 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . .54 5-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . .55 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 62 7-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 7-3 sim clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 18 list of figures motorola figure title page 7-8 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 7-9 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7-10 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . . 90 7-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . .92 7-13 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . . .92 7-14 interrupt status register 3 (int3). . . . . . . . . . . . . . . . . . . . . . .93 7-15 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 7-16 wait recovery from interrupt or break . . . . . . . . . . . . . . . . . . . 95 7-17 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . . 95 7-18 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7-19 stop mode recovery from interrupt or break . . . . . . . . . . . . . . 97 7-20 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7-21 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7-22 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . .100 8-1 x-tal oscillator external connections . . . . . . . . . . . . . . . . . . . 102 8-2 rc oscillator external connections . . . . . . . . . . . . . . . . . . . . 103 9-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9-2 low-voltage monitor mode entry flowchart. . . . . . . . . . . . . . 112 9-3 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9-4 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .114 9-5 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9-6 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9-7 monitor mode entry timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 119 10-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10-2 tim i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 10-3 pwm period and pulse width . . . . . . . . . . . . . . . . . . . . . . . . 128 10-4 tim status and control register (tsc) . . . . . . . . . . . . . . . . . 134 10-5 tim counter registers (tcnth:tcntl) . . . . . . . . . . . . . . . . 136 10-6 tim counter modulo registers (tmodh:tmodl). . . . . . . . . 137 10-7 tim channel status and control registers (tsc0:tsc1) . . .138 10-8 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 10-9 tim channel registers (tch0h/l:tch1h/l). . . . . . . . . . . . . 142 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola list of figures 19 figure title page 11-1 adc i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . .144 11-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11-3 adc status and control register (adscr) . . . . . . . . . . . . . . 148 11-4 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11-5 adc input clock register (adiclk) . . . . . . . . . . . . . . . . . . .151 12-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 154 12-2 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . . .156 12-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 157 12-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 12-5 port a input pull-up enable register (ptapue) . . . . . . . . . . 158 12-6 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . . .159 12-7 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 160 12-8 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12-9 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . . .162 12-10 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 163 12-11 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12-12 port d control register (pdcr) . . . . . . . . . . . . . . . . . . . . . . . 164 13-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .167 13-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13-3 irq status and control register (intscr) . . . . . . . . . . . . . . 169 13-4 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . .170 14-1 kbi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14-2 keyboard interrupt block diagram . . . . . . . . . . . . . . . . . . . . . 172 14-3 keyboard status and control register (kbscr) . . . . . . . . . . 175 14-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 176 15-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . .182 15-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . .183 16-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 16-2 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . .186 16-3 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . .187 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 20 list of figures motorola figure title page 17-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 191 17-2 break i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . 191 17-3 break status and control register (brkscr). . . . . . . . . . . . 193 17-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 194 17-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 194 17-6 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . 194 17-7 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . .196 18-1 rc vs. frequency (5v @25 c) . . . . . . . . . . . . . . . . . . . . . . . 202 18-2 rc vs. frequency (3v @25 c) . . . . . . . . . . . . . . . . . . . . . . . 205 18-3 typical operating i dd (mc68hc908jl3e/jk3e/jk1e), with all modules turned on (25 c) . . . . . . . . . . . . . . . . . 206 18-4 typical operating i dd (mc68hrc908jl3e/jk3e/jk1e), with all modules turned on (25 c) . . . . . . . . . . . . . . . . . 206 18-5 typical wait mode i dd (mc68hc908jl3e/jk3e/jk1e), with all modules turned off (25 c) . . . . . . . . . . . . . . . . . 207 18-6 typical wait mode i dd (mc68hrc908jl3e/jk3e/jk1e), with all modules turned off (25 c) . . . . . . . . . . . . . . . . . 207 19-1 20-pin pdip (case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19-2 20-pin soic (case #751d) . . . . . . . . . . . . . . . . . . . . . . . . . .212 19-3 28-pin pdip (case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19-4 28-pin soic (case #751f). . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19-5 48-pin lqfp (case #932) . . . . . . . . . . . . . . . . . . . . . . . . . . .214 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola list of tables 21 technical data ? mc68h(r)c908jl3e/jk3e/jk1e list of tables table title page 1-1 summary of device variations . . . . . . . . . . . . . . . . . . . . . . . . . 23 1-2 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 7-1 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 7-3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7-4 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 9-1 monitor mode entry requirements and options. . . . . . . . . . . 110 9-2 monitor mode vector differences . . . . . . . . . . . . . . . . . . . . . .113 9-3 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 113 9-4 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 116 9-5 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 116 9-6 iread (indexed read) command . . . . . . . . . . . . . . . . . . . . . 117 9-7 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . .117 9-8 readsp (read stack pointer) command . . . . . . . . . . . . . . .118 9-9 run (run user program) command . . . . . . . . . . . . . . . . . . . 118 10-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 10-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . .140 11-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 11-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 22 list of tables motorola table title page 12-1 port control register bits summary. . . . . . . . . . . . . . . . . . . . 155 12-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12-3 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12-4 port d pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 18-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .198 18-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 18-3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 18-4 dc electrical characteristics (5v) . . . . . . . . . . . . . . . . . . . . . 200 18-5 control timing (5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18-6 oscillator component specifications (5v) . . . . . . . . . . . . . . . 202 18-7 dc electrical characteristics (3v) . . . . . . . . . . . . . . . . . . . . . 203 18-8 control timing (3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 18-9 oscillator component specifications (3v) . . . . . . . . . . . . . . . 205 18-10 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18-11 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 20-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 a-1 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a-2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 219 a-3 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 a-4 oscillator component specifications . . . . . . . . . . . . . . . . . . .220 a-5 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 a-6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 a-7 mc68HLC908JL3E/jk3e/jk1e order numbers . . . . . . . . . . 223 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola general description 23 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.2 introduction the mc68h(r)c908jl3e is a member of the low-cost, high- performance m68hc08 family of 8-bit microcontroller units (mcus). the m68hc08 family is based on the customer-specified integrated circuit (csic) design strategy. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. table 1-1. summary of device variations device oscillator option flash memory size pin count mc68hc908jl3e x-tal 4096 bytes 28 mc68hrc908jl3e rc mc68hc908jk3e x-tal 4096 bytes 20 mc68hrc908jk3e rc mc68hc908jk1e x-tal 1536 bytes 20 mc68hrc908jk1e rc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 24 general description motorola all references to the mc68h(r)c908jl3e in this data book apply equally to the mc68h(r)c908jk3e and mc68h(r)c908jk1e, unless otherwise stated. 1.3 features features of the mc68h(r)c908jl3e include the following: emc enhanced version of mc68h(r)c908jl3/jk3/jk1 high-performance m68hc08 architecture fully upward-compatible object code with m6805, m146805, and m68hc05 families low-power design; fully static with stop and wait modes maximum internal bus frequency: ? 8-mhz at 5v operating voltage ? 4-mhz at 3v operating voltage oscillator options: ? crystal oscillator for mc68hc908jl3e/jk3e/jk1e ? rc oscillator for mc68hrc908jl3e/jk3e/jk1e user program flash memory with security 1 feature ? 4,096 bytes for mc68h(r)c908jl3e/jk3e ? 1,536 bytes for mc68h(r)c908jk1e 128 bytes of on-chip ram 2-channel, 16-bit timer interface module (tim) 12-channel, 8-bit analog-to-digital converter (adc) 23 general purpose i/o ports for mc68h(r)c908jl3e: ? 7 keyboard interrupt with internal pull-up (6 keyboard interrupt for mc68hc908jl3e) ? 10 led drivers (sink) ?2 25ma open-drain i/o with pull-up 1. no security feature is absolutely secure. however, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description features mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola general description 25 15 general purpose i/o ports for mc68h(r)c908jk3e/jk1e: ? 1 keyboard interrupt with internal pull-up (mc68hrc908jk3e/jk1e only) ? 4 led drivers (sink) ?2 25ma open-drain i/o with pull-up ? 10-channel adc system protection features: ? optional computer operating properly (cop) reset ? optional low-voltage detection with reset and selectable trip points for 3v and 5v operation ? illegal opcode detection with reset ? illegal address detection with reset master reset pin with internal pull-up and power-on reset irq1 with schmitt-trigger input and programmable pull-up 28-pin pdip, 28-pin soic, and 48-pin lqfp packages for mc68h(r)c908jl3e 20-pin pdip and 20-pin soic packages for mc68h(r)c908jk3e/jk1e features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 26 general description motorola 1.4 mcu block diagram figure 1-1 shows the structure of the mc68h(r)c908jl3e. figure 1-1. mcu block diagram system integration module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes user flash: user ram ? 128 bytes monitor rom ? 960 bytes user flash vector space ? 48 bytes external interrupt module internal bus * rst * irq1 power vss 2-channel timer interface module keyboard interrupt module 8-bit analog-to-digital converter module vdd adc reference ddrb portb ptb7/adc7 ptb6/adc6 ptb5/adc5 ptb4/adc4 ptb3/adc3 ptb2/adc2 ptb1/adc1 ptb0/adc0 ddra porta pta6/kbi6** pta5/kbi5** ? pta4/kbi4** ? pta3/kbi3** ? pta2/kbi2** ? pta1/kbi1** ? pta0/kbi0** ? low-voltage inhibit module * pin contains integrated pull-up device. ** pin contains programmable pull-up device. ? 25ma open-drain if output pin. ? led direct sink pin. osc1 osc2 x-tal oscillator rc oscillator ddrd portd ptd7 ** ?? ptd6 ** ?? ptd5/tch1 ptd4/tch0 ptd3/adc8 ? ptd2/adc9 ? ptd1/adc10 ptd0/adc11 computer operating properly module mc68h(r)c908jk1e ? 1,536 bytes power-on reset module break module # # # pins available on mc68h(r)c908jl3e only. mc68hrc908jl3e/jk3e/jk1e mc68hc908jl3e/jk3e/jk1e shared pin: mc68hrc908jl3e/jk3e/jk1e ? rcclk/pta6/kbi6 mc68h(r)c908jk3e/jl3e ? 4,096 bytes mc68hc908jl3e/jk3e/jk1e ? osc2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola general description 27 1.5 pin assignments figure 1-2. 28-pin pdip/soic pin assignment figure 1-3. 20-pin pdip/soic pin assignment 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 12 13 14 17 16 15 8 9 10 11 rst pta5/kbi5 ptd4/tch0 ptd5/tch1 ptd2/adc9 pta4/kbi4 ptd3/adc8 ptb0/adc0 ptb1/adc1 ptd1/adc10 ptb2/adc2 ptb3/adc3 ptd0/adc11 ptb4/adc4 irq1 pta0/kbi0 vss osc1 osc2/rcclk/pta6/kbi pta1/kbi1 vdd pta2/kbi2 pta3/kbi3 ptb7/adc7 ptb6/adc6 ptb5/adc5 ptd7 ptd6 mc68h(r)c908jl3e 1 2 3 4 5 6 7 20 19 18 17 16 15 14 13 12 11 8 9 10 rst ptd4/tch0 ptd5/tch1 ptd2/adc9 ptd3/adc8 ptb0/adc0 ptb1/adc1 ptb2/adc2 ptb3/adc3 ptb4/adc4 irq1 vss osc1 osc2/rcclk/pta6/kbi vdd ptb7/adc7 ptb6/adc6 ptb5/adc5 ptd7 ptd6 pins not available on 20-pin packages pta0/kbi0 ptd0/adc11 pta1/kbi1 ptd1/adc10 pta2/kbi2 pta3/kbi3 pta4/kbi4 pta5/kbi5 internal pads are unconnected. mc68h(r)c908jk3e/jk1e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 28 general description motorola figure 1-4. 48-pin lqfp pin assignment rst 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 14 15 16 17 18 19 20 21 22 36 32 31 30 29 28 27 26 13 nc pta3kbi3 ptb7/adc7 nc nc osc1 osc2/rcclk/pta6/kbi6 pta1/kbi1 nc vdd pta2/kbi2 ptd7 ptb6/adc6 nc nc ptb5/adc5 ptd6 ptb2/adc2 ptb3/adc3 ptd0/adc11 nc ptb4/adc4 nc nc nc nc ptd3/adc8 nc ptd1/adc10 ptb0/adc0 pta4/kbi4 ptd2/adc9 ptb1/adc1 nc 12 nc 25 nc 11 24 nc 23 35 34 33 irq1 pta0/kbi0 vss nc nc nc ptd5/tch1 ptd4/tch0 pta5/kbi5 nc 37 38 nc: no connection mc68h(r)c908jl3e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin functions mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola general description 29 1.6 pin functions description of the pin functions are provided in table 1-2 . note: on the mc68h(r)c908jk3e/jk1e, the following pins are not available: pta0, pta1, pta2, pta3, pta4, pta5, ptd0, and ptd1. table 1-2. pin functions pin name pin description in/out voltage level vdd power supply. in 5v or 3v vss power supply ground out 0v rst reset input, active low. with internal pull-up and schmitt trigger input. input vdd irq1 external irq pin. with software programmable internal pull-up and schmitt trigger input. this pin is also used for mode entry selection. input vdd to vdd+v hi osc1 x-tal or rc oscillator input. in analog osc2 mc68hc908jl3e/jk3e/jk1e: x-tal oscillator output, this is the inverting osc1 signal. out analog mc68hrc908jl3e/jk3e/jk1e: default is rc oscillator clock output, rcclk. shared with pta6/kbi6, with programmable pull-up. in/out vdd pta[0:6] 7-bit general purpose i/o port. in/out vdd shared with 7 keyboard interrupts kbi[0:6]. in vdd each pin has programmable internal pull-up device. in vdd pta[0:5] have led direct sink capability in vss ptb[0:7] 8-bit general purpose i/o port. in/out vdd shared with 8 adc inputs, adc[0:7]. in analog ptd[0:7] 8-bit general purpose i/o port. in/out vdd ptd[3:0] shared with 4 adc inputs, adc[8:11]. input analog ptd[4:5] shared with tim channels, tch0 and tch1. in/out vdd ptd[2:3], ptd[6:7] have led direct sink capability in vss ptd[6:7] can be configured as 25ma open-drain output with pull-up. in/out vdd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 30 general description motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola memory map 31 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 4,096 bytes of user flash ? mc68h(r)c908jl3e/jk3e 1,536 bytes of user flash ? mc68h(r)c908jk1e 128 bytes of ram 48 bytes of user-defined vectors 960 bytes of monitor rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 32 memory map motorola $0000 $003f i/o registers 64 bytes $0040 $007f reserved 64 bytes $0080 $00ff ram 128 bytes $0100 $ebff unimplemented 60,160 bytes unimplemented 62,720 bytes $0100 $f5ff $ec00 $fbff flash memory mc68h(r)c908jl3e/jk3e 4,096 bytes flash memory mc68h(r)c908jk1e 1,536 bytes $f600 $fbff $fc00 $fdff monitor rom 512 bytes $fe00 break status register (bsr) $fe01 reset status register (rsr) $fe02 reserved (ubar) $fe03 break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 reserved $fe08 flash control register (flcr) $fe09 flash block protect register (flbpr) $fe0a reserved $fe0b reserved $fe0c break address high register (brkh) $fe0d break address low register (brkl) $fe0e break status and control register (brkscr) $fe0f reserved $fe10 $ffcf monitor rom 448 bytes $ffd0 $ffff user vectors 48 bytes figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola memory map 33 2.3 i/o section addresses $0000?$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have the following addresses: $fe00; break status register, bsr $fe01; reset status register, rsr $fe02; reserved $fe03; break flag control register, bfcr $fe04; interrupt status register 1, int1 $fe05; interrupt status register 2, int2 $fe06; interrupt status register 3, int3 $fe07; reserved $fe08; flash control register, flcr $fe09; flash block protect register, flbpr $fe0a; reserved $fe0b; reserved $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; reserved $ffff; cop control register, copctl 2.4 monitor rom the 960 bytes at addresses $fc00?$fdff and $fe10?$ffcf are reserved rom addresses that contain the instructions for the monitor functions. (see section 9. monitor rom (mon) .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 34 memory map motorola addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 unimplemented read: write: $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 unimplemented read: write: $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 $0009 unimplemented read: write: $000a port d control register (pdcr) read: 0000 slowd7 slowd6 ptdpu7 ptdpu6 write: reset:00000000 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map monitor rom mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola memory map 35 $000b $000c unimplemented read: write: $000d port a input pull-up enable register (ptapue) read: pta6en ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e $0019 unimplemented read: write: $001a keyboard status and control register (kbscr) read: 0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $001c unimplemented read: write: $001d irq status and control register (intscr) read: 0000irqf10 imask1 mode1 write: ack1 reset:00000000 $001e configuration register 2 (config2) ? read: irqpudrrlvit1lvit0rrr write: reset:0000*0*000 $001f configuration register 1 (config1) ? read: coprs r r lvid r ssrec stop copd write: reset:00000000 ? one-time writable register after each reset. * lvit1 and lvit0 reset to logic 0 by a power-on reset (por) only. $0020 tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 36 memory map motorola $0021 tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $0022 tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0027 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map monitor rom mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola memory map 37 $002b $003b unimplemented read: write: $003c adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $003e adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 $003f unimplemented read: write: $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 note: writing a logic 0 clears sbsw. $fe01 reset status register (rsr) read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 38 memory map motorola $fe05 interrupt status register 2 (int2) read: if14 0000000 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 0000000if15 write:rrrrrrrr reset:00000000 $fe07 reserved read: rrrrrrrr write: $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 $fe0a $fe0b reserved read: rrrrrrrr write: $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 5) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map monitor rom mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola memory map 39 . table 2-1. vector addresses vector priority int flag address vector lowest highest ? $ffd0 $ffdd not used if15 $ffde adc conversion complete vector (high) $ffdf adc conversion complete vector (low) if14 $ffe0 keyboard vector (high) $ffe1 keyboard vector (low) if13 if6 ?not used if5 $fff2 tim overflow vector (high) $fff3 tim overflow vector (low) if4 $fff4 tim channel 1 vector (high) $fff5 tim channel 1 vector (low) if3 $fff6 tim channel 0 vector (high) $fff7 tim channel 0 vector (low) if2 ? not used if1 $fffa irq 1 vector (high) $fffb irq 1 vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) $ffff reset vector (low) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 40 memory map motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola random-access memory (ram) 41 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 introduction this section describes the 128 bytes of ram. 3.3 functional description addresses $0080 through $00ff are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 128 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access efficiently all page zero ram locations. page zero ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . random-access memory (ram) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 42 random-access memory (ram) motorola during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola flash memory (flash) 43 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 4. flash memory (flash) 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.5 flash page erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.8 flash protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.9 flash block protect register . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.2 introduction this section describes the operation of the embedded flash memory. the flash memory can be read, programmed, and erased from a single external supply. the program and erase operations are enabled through the use of an internal charge pump. device flash memory size (bytes) memory address range mc68h(r)c908jl3e 4,096 $ec00?$fbff mc68h(r)c908jk3e 4,096 $ec00?$fbff mc68h(r)c908jk1e 1,536 $f600?$fbff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 44 flash memory (flash) motorola 4.3 functional description the flash memory consists of an array of 4,096 or 1,536 bytes with an additional 48 bytes for user vectors. the minimum size of flash memory that can be erased is 64 bytes (a page); and the maximum size of flash memory that can be programmed in a program cycle is 32 bytes (a row). program and erase operations are facilitated through control bits in the flash control register (flcr). details for these operations appear later in this section. the address ranges for the user memory and vectors are: $ec00?$fbff; user memory; 4,096 bytes; mc68h(r)c908jl3e/jk3e $f600?$fbff; user memory; 1,536 bytes; mc68h(r)c908jk1e $ffd0?$ffff; user interrupt vectors; 48 bytes note: an erased bit reads as logic 1 and a programmed bit reads as logic 0. a security feature prevents viewing of the flash contents. 1 addr.register name bit 7654321bit 0 $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 = unimplemented figure 4-1. flash i/o register summary 1. no security feature is absolutely secure. however, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) flash control register mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola flash memory (flash) 45 4.4 flash control register the flash control register controls flash program and erase operations. hven ? high voltage enable bit this read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. it can only be set if either pgm=1 or erase=1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit configures the memory for mass erase operation or page erase operation when the erase bit is set. 1 = mass erase operation selected 0 = page erase operation selected erase ? erase control bit this read/write bit configures the memory for erase operation. this bit and the pgm bit should not be set to 1 at the same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit configures the memory for program operation. this bit and the erase bit should not be set to 1 at the same time. 1 = program operation selected 0 = program operation not selected address: $fe08 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 figure 4-2. flash control register (flcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 46 flash memory (flash) motorola 4.5 flash page erase operation use the following procedure to erase a page of flash memory. a page consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80 or $xxc0. the 48-byte user interrupt vectors area also forms a page. any page within the 4k bytes user memory area ($ec00?$fbff) can be erased alone. the 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. mass erase is required to erase this page. 1. set the erase bit and clear the mass bit in the flash control register. 2. write any data to any flash address within the page address range desired. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time t erase (1ms). 6. clear the erase bit. 7. wait for a time, t nvh (5 s). 8. clear the hven bit. 9. after time, t rcv (1 s) , the memory can be accessed in read mode again. note: programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) flash mass erase operation mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola flash memory (flash) 47 4.6 flash mass erase operation use the following procedure to erase the entire flash memory: 1. set both the erase bit and the mass bit in the flash control register. 2. write any data to any flash location within the flash memory address range. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time t merase (4ms). 6. clear the erase bit. 7. wait for a time, t nvh1 (100 s). 8. clear the hven bit. 9. after time, t rcv (1 s) , the memory can be accessed in read mode again. note: programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 48 flash memory (flash) motorola 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $xx60, $xx80, $xxa0, $xxc0 or $xxe0. use this step-by-step procedure to program a row of flash memory: ( figure 4-3 shows a flowchart of the programming algorithm.) 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. write any data to any flash location within the address range of the row to be programmed. 3. wait for a time, t nvs (10 s). 4. set the hven bit. 5. wait for a time, t pgs (5 s). 6. write data to the byte being programmed. 7. wait for time, t prog (30 s). 8. repeat step 6 and 7 until all the bytes within the row are programmed. 9. clear the pgm bit. 10. wait for time, t nvh (5 s). 11. clear the hven bit. 12. after time, t rcv (1 s), the memory can be accessed in read mode again. this program sequence is repeated throughout the memory until all data is programmed. note: the time between each flash address change (step 6 to step 6), or the time between the last flash addressed programmed to clearing the pgm bit (step 6 to step 10), must not exceed the maximum programming time, t prog max. note: programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) flash program operation mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola flash memory (flash) 49 figure 4-3. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (32 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 50 flash memory (flash) motorola 4.8 flash protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. 4.9 flash block protect register the flash block protect register is implemented as an 8-bit i/o register. the value in this register determines the starting address of the protected range within the flash memory. bpr[7:0] ? flash block protect register bit 7 to bit 0 bpr[7:1] represent bits [12:6] of a 16-bit memory address. bits [15:13] are logic 1?s and bits [5:0] are logic 0?s. bpr0 is used only for bpr[7:0] = $ff, for no block protection. address: $fe09 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:00000000 figure 4-4. flash block protect register (flbpr) 16-bit memory address start address of flash block protect 111 000000 bpr[7:1] f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) flash block protect register mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola flash memory (flash) 51 the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this start address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be xx00, xx40, xx80, or xxc0 (at page boundaries ? 64 bytes) within the flash memory. examples of protect start address: bpr[7:0] start of address of protect range $00?$60 the entire flash memory is protected. $62 or $63 ( 0110 001x ) $ec40 (111 0 1100 01 00 0000) $64 or $65 ( 0110 010x ) $ec80 (111 0 1100 10 00 0000) $68 or $69 ( 0110 100x ) $ed00 (111 0 1101 00 00 0000) and so on... $de or $df ( 1101 111x ) $fbc0 (111 1 1011 11 00 0000) $fe ( 1111 1110 ) $ffc0 (111 1 1111 11 00 0000) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . flash memory (flash) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 52 flash memory (flash) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola configuration register (config) 53 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5.2 introduction this section describes the configuration registers (config1 and config2). the configuration registers enables or disables the following options: stop mode recovery time (32 2oscout cycles or 4096 2oscout cycles) stop instruction computer operating properly module (cop) cop reset period (coprs), (2 13 ?2 4 ) 2oscout or (2 18 ?2 4 ) 2oscout enable lvi circuit select lvi trip voltage f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 54 configuration register (config) motorola 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be written once after each reset. all of the configuration register bits are cleared during reset. since the various options affect the operation of the mcu it is recommended that this register be written immediately after reset. the configuration register is located at $001e and $001f, and may be read at anytim e. note: the config registers are one-time writable by the user after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 5-1 and figure 5-2 . irqpud ? irq1 pin pull-up control bit 1 = internal pull-up is disconnected 0 = internal pull-up is connected between irq1 pin and v dd lvit1, lvit0 ? low voltage inhibit trip voltage selection bits detail description of the lvi control signals is given in section 16. low voltage inhibit (lvi) address: $001e bit 7654321bit 0 read: irqpudrrlvit1lvit0rrr write: reset:000 not affected not affected 000 por:00000000 r=reserved figure 5-1. configuration register 2 (config2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola configuration register (config) 55 coprs ? cop reset period selection bit 1 = cop reset cycle is (2 13 ? 2 4 ) 2oscout 0 = cop reset cycle is (2 18 ? 2 4 ) 2oscout lvid ? low voltage inhibit disable bit 1 = low voltage inhibit disabled 0 = low voltage inhibit enabled ssrec ? short stop recovery bit ssrec enables the cpu to exit stop mode with a delay of 32 2oscout cycles instead of a 4096 2oscout cycle delay. 1 = stop mode recovery after 32 2oscout cycles 0 = stop mode recovery after 4096 2oscout cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal, do not set the ssrec bit. stop ? stop instruction enable stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 15. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: coprs r r lvid r ssrec stop copd write: reset:00000000 r=reserved figure 5-2. configuration register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 56 configuration register (config) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 57 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . .62 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 6.7 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 introduction the m68hc08 cpu (central processor unit) is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 58 central processor unit (cpu) motorola 6.3 features object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu registers are not part of the memory map. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 59 figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 60 central processor unit (cpu) motorola 6.4.2 index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 61 note: the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. program counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 62 central processor unit (cpu) motorola 6.4.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add- with-carry (adc) operation. the half-carry flag is required for binary- coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 63 note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 64 central processor unit (cpu) motorola 6.5 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock 6.6.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu during break interrupts mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 65 6.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary table 6-1 provides a summary of the m68hc08 instruction set. 6.9 opcode map the opcode map is provided in table 6-2 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 66 central processor unit (cpu) motorola table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ? ? ? ? ? ? imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 67 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v)=0??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v)=1??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 68 central processor unit (cpu) motorola brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 69 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ??? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a)?1 or m (m)?1 or x (x)?1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 70 central processor unit (cpu) motorola eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x (m:m + 1) 0?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 71 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ??0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ??????inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 72 central processor unit (cpu) motorola ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) opcode map mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 73 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 74 central processor unit (cpu) motorola a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressing mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 6-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola central processor unit (cpu) 75 central processor unit (cpu) opcode map table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789 abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3 ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3 ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3 ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3 ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 tap 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3 ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3 ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3 ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3 ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3 ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3 ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3 ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3 ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3 ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3 ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3 ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3 ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 76 central processor unit (cpu) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 77 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 7. system integration module (sim) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 81 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 7.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . .81 7.4 reset and system initialization. . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.4.2 active resets from internal sources . . . . . . . . . . . . . . . . . . 83 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 7.4.2.2 computer operating properly (cop) reset. . . . . . . . . . . 85 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.4.2.5 lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 7.5.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . 86 7.5.2 sim counter during stop mode recovery . . . . . . . . . . . . . . 86 7.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . .87 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.6.2 interrupt status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.6.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . 92 7.6.2.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . .94 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 78 system integration module (sim) motorola 7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8.1 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . .97 7.8.2 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . 98 7.8.3 break flag control register (bfcr) . . . . . . . . . . . . . . . . . 100 7.2 introduction this section describes the system integration module (sim), which supports up to 24 external and/or internal interrupts. together with the cpu, the sim controls all mcu activities. a block diagram of the sim is shown in figure 7-1 . figure 7-2 is a summary of the sim i/o registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) introduction mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 79 figure 7-1. sim block diagram table 7-1. signal name conventions signal name description 2oscout buffered clock from the x-tal oscillator circuit or the rc oscillator circuit. oscout the 2oscout frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = 2oscout 4) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from oscillator) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock 2oscout (from oscillator) 2 usb reset (from usb module) vdd internal pull-up f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 80 system integration module (sim) motorola addr.register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: note reset:00000000 note: writing a logic 0 clears sbsw. $fe01 reset status register (rsr) read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset: $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 0000000 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 0000000if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 7-2. sim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim bus clock control and generation mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 81 7.3 sim bus clock control and generation the bus clock generator provides system clock signals for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, oscout, as shown in figure 7-3 . figure 7-3. sim clock signals 7.3.1 bus timing in user mode , the internal bus frequency is the oscillator frequency (2oscout) divided by four. 7.3.2 clock start-up from por when the power-on reset module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 2oscout cycle por time-out has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the time-out. 7.3.3 clocks in stop mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows 2oscout to clock the sim counter. the cpu and peripheral clocks do not become active until after the stop delay time-out. this time-out is selectable as 4096 or 32 2oscout cycles. (see 7.7.2 stop mode .) in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. 2 bus clock generators sim sim counter from oscillator from oscillator oscout 2oscout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 82 system integration module (sim) motorola 7.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?$ffff ($fefe?$feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 7.5 sim counter ), but an external reset does not. each of the resets sets a corresponding bit in the reset status register (rsr). (see 7.8 sim registers .) 7.4.1 external pin reset the rst pin circuits include an internal pull-up device. pulling the asynchronous rst pin low halts all processing. the pin bit of the reset status register (rsr) is set as long as rst is held low for a minimum of 67 2oscout cycles, assuming that the por was not the source of the reset. see table 7-2 for details. figure 7-4 shows the relative timing. figure 7-4. external reset timing table 7-2. pin bit set timing reset type number of cycles required to set pin por 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l 2oscout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 83 7.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 2oscout cycles to allow resetting of external peripherals. the internal reset signal irst continues to be asserted for an additional 32 cycles ( figure 7-5 ). an internal reset can be caused by an illegal address, illegal opcode, cop time-out, or por. (see figure 7-6 . sources of internal reset .) note that for por resets, the sim cycles through 4096 2oscout cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 7-5 . figure 7-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 7-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high 2oscout illegal address rst illegal opcode rst coprst por lvi internal reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 84 system integration module (sim) motorola 7.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 2oscout cycles. sixty-four 2oscout cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscillator to drive 2oscout. internal clocks to the cpu and modules are held inactive for 4096 2oscout cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the reset status register (rsr) is set and all other bits in the register are cleared. figure 7-7. por recovery porrst osc1 2oscout oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 85 7.4.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the reset status register (rsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module time-out, write any value to location $ffff. writing to location $ffff clears the cop counter and stages 12 through 5 of the sim counter. the sim counter output, which occurs at least every (2 12 ? 2 4 ) 2oscout cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time-out. the cop module is disabled if the rst pin or the irq1 pin is held at v dd +v hi while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq1 pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v dd +v hi on the rst pin disables the cop module. 7.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the reset status register (rsr) and causes a reset. if the stop enable bit, stop, in the mask option register is logic zero, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 7.4.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the reset status register (rsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 86 system integration module (sim) motorola 7.4.2.5 lvi reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the lvi trip voltage v trip . the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rstb) is held low while the sim counter counts out 4096 2oscout cycles. sixty- four 2oscout cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. the sim actively pulls down the (rstb) pin for all internal reset sources. 7.5 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the clock for the cop module. the sim counter is clocked by the falling edge of 2oscout. 7.5.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. 7.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the mask option register. if the ssrec bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 2oscout cycles down to 32 2oscout cycles. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared in the configuration register (config). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 87 7.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 7.7.2 stop mode for details.) the sim counter is free-running after all reset states. (see 7.4.2 active resets from internal sources for counter control and internal reset recovery sequences.) 7.6 exception control normal, sequential program execution can be changed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 7.6.1 interrupts an interrupt temporarily changes the sequence of program execution to respond to a particular event. figure 7-8 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 88 system integration module (sim) motorola figure 7-8. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? timer interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 89 at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 7-9 shows interrupt entry timing. figure 7-10 shows interrupt recovery timing. figure 7-9 . interrupt entry figure 7-10. interrupt recovery 7.6.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[15:8] pc ? 1[7:0] opcode operand i bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 90 system integration module (sim) motorola if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 7-11 demonstrates what happens when two interrupts are pending. if an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 7-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 91 7.6.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 7.6.2 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 7-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 7-3. interrupt sources priority source flag mask 1(1) int register flag vector address highest reset ? ? ? $fffe?$ffff swi instruction ? ? ? $fffc?$fffd irq 1 pin irqf1 imask1 if1 $fffa?$fffb timer channel 0 interrupt ch0f ch0ie if3 $fff6?$fff7 timer channel 1 interrupt ch1f ch1ie if4 $fff4?$fff5 timer overflow interrupt tof toie if5 $fff2?$fff3 keyboard interrupt keyf imaskk if14 $ffe0?$ffe1 lowest adc conversion complete interrupt coco aien if15 $ffde?$ffdf notes : 1. the i bit in the condition code register is a global mask for all interrupts sources except the swi instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 92 system integration module (sim) motorola 7.6.2.1 interrupt status register 1 if1, if3 to if5 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 7-3 . 1 = interrupt request present 0 = no interrupt request present bit 0, 1, 3 and 7 ? always read 0 7.6.2.2 interrupt status register 2 if14 ? interrupt flags this flag indicates the presence of interrupt requests from the sources shown in table 7-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 to 6 ? always read 0 address: $fe04 bit 7654321bit 0 read: 0 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 7-12. interrupt status register 1 (int1) address: $fe05 bit 7654321bit 0 read: if14 0000000 write:rrrrrrrr reset:00000000 r= reserved figure 7-13. interrupt status register 2 (int2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 93 7.6.2.3 interrupt status register 3 if15 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 7-3 . 1 = interrupt request present 0 = no interrupt request present bit 1 to 7 ? always read 0 7.6.3 reset all reset sources always have equal and highest priority and cannot be arbitrated. 7.6.4 break interrupts the break module can stop normal program flow at a software- programmable break point by asserting its break interrupt output. (see section 17. break module (break) .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. address: $fe06 bit 7654321bit 0 read: 0000000if15 write:rrrrrrrr reset:00000000 r= reserved figure 7-14. interrupt status register 3 (int3) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 94 system integration module (sim) motorola 7.6.5 status flag protection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (bcfe) in the break flag control register (bfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing status flag information. setting the bcfe bit enables the clearing mechanisms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 7.7 low-power modes executing the wait or stop instruction puts the mcu in a low-power- consumption mode for standby situations. the sim holds the cpu in a non-clocked state. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 7.7.1 wait mode in wait mode, the cpu clocks are inactive while the peripheral clocks continue to run. figure 7-15 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wait instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 95 wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the break status register (bsr). if the cop disable bit, copd, in the mask option register is logic zero, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 7-15. wait mode entry timing figure 7-16 and figure 7-17 show the timing for wait recovery. figure 7-16. wait recovery from interrupt or break figure 7-17. wait recovery from internal reset wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 2oscout 32 cycles 32 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 96 system integration module (sim) motorola 7.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the oscillator signals (oscout and 2oscout) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configuration register (config). if ssrec is set, stop recovery is reduced from the normal delay of 4096 2oscout cycles down to 32. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. note: external crystal applications should use the full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the break status register (bsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 7-18 shows stop mode entry timing. note: to minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0. figure 7-18. stop mode entry timing stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 97 figure 7-19. stop mode recovery from interrupt or break 7.8 sim registers the sim has three memory mapped registers. table 7-4 shows the mapping of these registers. 7.8.1 break status register (bsr) the break status register contains a flag to indicate that a break caused an exit from stop or wait mode. 2oscout int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period table 7-4. sim registers address register access mode $fe00 bsr user $fe01 rsr user $fe03 bfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a logic zero clears sbsw. figure 7-20. break status register (bsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 98 system integration module (sim) motorola sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic zero to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example of this. writing zero to the sbsw bit clears it. 7.8.2 reset status register (rsr) this register contains six flags that show the source of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola system integration module (sim) 99 por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while irq 1 = v dd 0 = por or read of srsr lvi ? low voltage inhibit reset bit 1 = last reset caused by lvi circuit 0 = por or read of srsr address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 = unimplemented figure 7-21. reset status register (rsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 100 system integration module (sim) motorola 7.8.3 break flag control register (bfcr) the break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 7-22. break flag control register (bfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola oscillator (osc) 101 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 8. oscillator (osc) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 8.3 x-tal oscillator (mc68hc908jl3e/jk3e/jk1e). . . . . . . . . . . 102 8.4 rc oscillator (mc68hrc908jl3e/jk3e/jk1e) . . . . . . . . . . 103 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 8.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 104 8.5.2 crystal amplifier output pin (osc2/pta6/rcclk). . . . . . 104 8.5.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 104 8.5.4 x-tal oscillator clock (xtalclk). . . . . . . . . . . . . . . . . . . . 104 8.5.5 rc oscillator clock (rcclk). . . . . . . . . . . . . . . . . . . . . . . 105 8.5.6 oscillator out 2 (2oscout) . . . . . . . . . . . . . . . . . . . . . . . 105 8.5.7 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.7 oscillator during break mode. . . . . . . . . . . . . . . . . . . . . . . . . 106 8.2 introduction the oscillator module provides the reference clock for the mcu system and bus. two types of oscillator modules are available: mc68hc908jl3e/jk3e/jk1e ? built-in oscillator module (x-tal) that requires an external crystal or ceramic-resonator. this option also allows an external clock that can be driven directly into osc1. mc68hrc908jl3e/jk3e/jk1e ? built-in oscillator module (rc) that requires an external rc connection only. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 102 oscillator (osc) motorola 8.3 x-tal oscillator (mc68hc908jl3e/jk3e/jk1e) the x-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. in its typical configuration, the x-tal oscillator is connected in a pierce oscillator configuration, as shown in figure 8-1 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) figure 8-1. x-tal oscillator external connections c 1 c 2 simoscen xtalclk r b x 1 r s * *r s can be zero (shorted) when used with higher-frequency crystals. mcu from sim refer to manufacturer?s data. osc2 osc1 2 oscout 2oscout to sim to sim see section 18. for component value requirements. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) rc oscillator (mc68hrc908jl3e/jk3e/jk1e) mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola oscillator (osc) 103 the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer?s data for more information. 8.4 rc oscillator (mc68hrc908jl3e/jk3e/jk1e) the rc oscillator circuit is designed for use with external r and c to provide a clock source with tolerance less than 10%. in its typical configuration, the rc oscillator requires two external components, one r and one c. component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. the oscillator configuration uses two components: c ext r ext figure 8-2. rc oscillator external connections mcu r ext c ext simoscen osc1 ext-rc oscillator en rcclk 2 oscout 2oscout to sim from sim v dd pta6 i/o 0 1 pta6 pta6en pta6/rcclk (osc2) to sim see section 18. for component value requirements. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 104 oscillator (osc) motorola 8.5 i/o signals the following paragraphs describe the oscillator i/o signals. 8.5.1 crystal amplifier input pin (osc1) osc1 pin is an input to the crystal oscillator amplifier or the input to the rc oscillator circuit. 8.5.2 crystal amplifier output pin (osc2/pta6/rcclk) for the x-tal oscillator device , osc2 pin is the output of the crystal oscillator inverting amplifier. for the rc oscillator device, osc2 pin can be configured as a general purpose i/o pin pta6, or the output of the internal rc oscillator clock, rcclk. 8.5.3 oscillator enable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables/disables the x-tal oscillator circuit or the rc-oscillator. 8.5.4 x-tal oscillator clock (xtalclk) xtalclk is the x-tal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 8-1 shows only the logical relation of xtalclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of xtalclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of xtalclk can be unstable at start-up. device oscillator osc2 pin function mc68hc908jl3e/jk3e/jk1e x-tal inverting osc1 mc68hrc908jl3e/jk3e/jk1e rc controlled by pta6en bit in ptapuer ($0d) pta6en = 0: rcclk output pta6en = 1: pta6 i/o f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) low power modes mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola oscillator (osc) 105 8.5.5 rc oscillator clock (rcclk) rcclk is the rc oscillator output signal. its frequency is directly proportional to the time constant of the external r and c. figure 8-2 shows only the logical relation of rcclk to osc1 and may not represent the actual circuitry. 8.5.6 oscillator out 2 (2oscout) 2oscout is same as the input clock (xtalclk or rcclk). this signal is driven to the sim module and is used to determine the cop cycles. 8.5.7 oscillator out (oscout) the frequency of this signal is equal to half of the 2oscout, this signal is driven to the sim for generation of the bus clocks used by the cpu and other modules on the mcu. oscout will be divided again in the sim and results in the internal bus frequency being one fourth of the xtalclk or rcclk frequency. 8.6 low power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 8.6.1 wait mode the wait instruction has no effect on the oscillator logic. oscout and 2oscout continues to drive to the sim module. 8.6.2 stop mode the stop instruction disables the xtalclk or the rcclk output, hence oscout and 2oscout. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . oscillator (osc) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 106 oscillator (osc) motorola 8.7 oscillator during break mode the oscillator continues to drive oscout and 2oscout when the device enters the break state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola monitor rom (mon) 107 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 9. monitor rom (mon) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.4.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9.4.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.4.4 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.4.5 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 9.4.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer. this mode is also used for programming and erasing of flash memory in the mcu. monitor mode entry can be achieved without use of the higher test voltage, v dd +v hi , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements for in-circuit programming. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 108 monitor rom (mon) motorola 9.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial communication between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory programming interface 960 bytes monitor rom code size monitor mode entry without high voltage, v dd +v hi , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v dd +v hi , is applied to irq 1 9.4 functional description the monitor rom receives and executes commands from a host computer. figure 9-1 shows a example circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute host-computer code in ram while most mcu pins retain normal operating mode functions. all communication between the host computer and the mcu is through the ptb0 pin. a level-shifting and multiplexing interface is required between ptb0 and the host computer. ptb0 is used in a wired-or configuration and requires a pull-up resistor. 1. no security feature is absolutely secure. however, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola monitor rom (mon) 109 figure 9-1. monitor mode circuit notes: 1. monitor mode entry method: sw1: position a ? high voltage entry (v tst ) clock source must be ext osc or xtal circuit. bus clock depends on sw2. sw1: position b ? reset vector must be blank ($fffe = $ffff = $ff) bus clock = osc1 4. 2. affects high voltage entry to monitor mode only (sw1 at position a): sw2: position c ? bus clock = osc1 4 sw2: position d ? bus clock = osc1 2 5. see table 18-4 for v dd + v hi voltage level requirements. 10m rst irq osc1 osc2 v ss ptb0 20 pf 20 pf 0.1 f 9.8304mhz ptb1 v dd 0.1 f v dd ptb2 v dd 10 k ptb3 v dd 10 k 10 k sw2 c d v dd (see note 2) a b xtal circuit 16 15 2 6 v dd max232 v+ v? v dd 10 k c1+ c1? 5 4 c2+ c2? + 3 1 1 f + + + 8 7 db9 2 3 5 10 9 + 1 2 3 4 5 6 74hc125 74hc125 1 k v dd + v hi v cc gnd 1 f 1 f 1 f 1 f 8.5 v v dd 10 k 10 k (50% duty) osc1 (see note 1) sw1 v dd osc1 osc2 see figure 18-1 for component values vs. frequency. h(r)c908jl3e h(r)c908jk3e h(r)c908jk1e ext osc osc2 rc circuit for mc68hc908jl3e/jk3e/jk1e sw1 at position a or b for mc68hrc908jl3e/jk3e/jk1e sw1 must be at position a for mc68hc908jl3e/jk3e/jk1e sw1 at position a or b for mc68hrc908jl3e/jk3e/jk1e sw1 must be at position b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 110 monitor rom (mon) motorola 9.4.1 entering monitor mode table 9-1 shows the pin conditions for entering monitor mode. as specified in the table, monitor mode may be entered after a por and will allow communication at 9600 baud provided one of the following sets of conditions is met: 1. if irq1 = v dd + v hi : ? clock on osc1 is 4.9125mhz (ext osc or xtal) ?ptb3 = low 2. if irq1 = v dd + v hi : ? clock on osc1 is 9.8304mhz (ext osc or xtal) ? ptb3 = high 3. if $fffe & $ffff is blank (contains $ff): ? clock on osc1 is 9.8304mhz (ext osc or xtal or rc) ?irq1 = v dd table 9-1. monitor mode entry requirements and options irq 1 $fffe and $ffff ptb3 (1) ptb2 ptb1 ptb0 osc1 frequency bus frequency comments v dd + v hi (2) x 0011 4.9152mhz 2.4576mhz (osc1 2) high-voltage entry to monitor mode. (3) 9600 baud communication on ptb0. cop disabled. v dd + v hi x 1011 9.8304mhz 2.4576mhz (osc1 4) v dd blank (contain $ff) xxx1 9.8304mhz 2.4576mhz (osc1 4) low-voltage entry to monitor mode. (4) 9600 baud communication on ptb0. cop disabled. v dd not blank xxxx at desired frequency osc1 4 enters user mode. notes : 1. ptb3 = 0: bypasses the divide-by-two prescaler to sim when using v dd + v hi for monitor mode entry. the osc1 clock must be 50% duty cycle for this condition. 2. see table 18-4 for v dd + v hi voltage level requirements. 3. for irq1 = v dd + v hi : mc68hrc908jl3e/jk3e/jk1e ? clock must be ext osc. mc68hc908jl3e/jk3e/jk1e ? clock can be ext osc or xtal. 4. for irq1 = v dd : mc68hrc908jl3e/jk3e/jk1e ? clock must be rc osc. mc68hc908jl3e/jk3e/jk1e ? clock can be ext osc or xtal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola monitor rom (mon) 111 if v dd +v hi is applied to irq1 and ptb3 is low upon monitor mode entry ( table 9-1 condition set 1), the bus frequency is a divide-by-two of the clock input to osc1. if ptb3 is high with v dd +v hi applied to irq1 upon monitor mode entry ( table 9-1 condition set 2), the bus frequency is a divide-by-four of the clock input to osc1. holding the ptb3 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if v dd +v hi is applied to irq1 . in this event, the oscout frequency is equal to the 2oscout frequency, and osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. entering monitor mode with v dd +v hi on irq1 , the cop is disabled as long as v dd +v hi is applied to either the irq1 or the rst . (see section 7. system integration module (sim) for more information on modes of operation.) if entering monitor mode without high voltage on irq 1 and reset vector being blank ($fffe and $ffff) ( table 9-1 condition set 3, where applied voltage is v dd ), then all port b pin requirements and conditions, including the ptb3 frequency divisor selection, are not in effect. this is to reduce circuit requirements when performing in-circuit programming. entering monitor mode with the reset vector being blank, the cop is always disabled regardless of the state of irq1 or the rst . figure 9-2 . shows a simplified diagram of the monitor mode entry when the reset vector is blank and irq1 = v dd . an osc1 frequency of 9.8304mhz is required for a baud rate of 9600. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 112 monitor rom (mon) motorola figure 9-2. low-voltage monitor mode entry flowchart enter monitor mode with the pin configuration shown above by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the values on the specified pins can change. once out of reset, the mcu waits for the host to send eight security bytes. (see 9.5 security .) after the security bytes, the mcu sends a break signal (10 consecutive logic zeros) to the host, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow the host to determine the necessary baud rate. in monitor mode, the mcu uses different vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. is vector blank? por triggered? normal user mode monitor mode execute monitor code no no yes yes por reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola monitor rom (mon) 113 table 9-2 is a summary of the vector differences between user mode and monitor mode. when the host computer has completed downloading code into the mcu ram, the host then sends a run command, which executes an rti, which sends control to the address on the stack pointer. 9.4.2 baud rate the communication baud rate is dependant on oscillator frequency. the state of ptb3 also affects baud rate if entry to monitor mode is by irq1 = v dd +v hi . when ptb3 is high, the divide by ratio is 1024. if the ptb3 pin is at logic zero upon entry into monitor mode, the divide by ratio is 512. table 9-2. monitor mode vector differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) $fefe $feff $fefc $fefd $fefc $fefd notes: 1. if the high voltage (v dd + v hi ) is removed from the irq 1 pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. table 9-3. monitor baud rate selection monitor mode entry by: input clock frequency ptb3 baud rate irq1 = v dd + v hi 4.9152 mhz 0 9600 bps 9.8304 mhz 1 9600 bps 4.9152 mhz 1 4800 bps blank reset vector, irq1 = v dd 9.8304 mhz x 9600 bps 4.9152 mhz x 4800 bps f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 114 monitor rom (mon) motorola 9.4.3 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 9-3 and figure 9-4 .) figure 9-3. monitor data format figure 9-4. sample monitor waveforms the data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. transmit and receive baud rates must be identical. 9.4.4 echoing as shown in figure 9-5 , the monitor rom immediately echoes each received byte back to the ptb0 pin for error checking. figure 9-5. read transaction any result of a command appears after the echo of the last byte of the command. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3bit 4bit 5bit 6bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola monitor rom (mon) 115 9.4.5 break signal a start bit followed by nine low bits is a break signal. (see figure 9-6.) when the monitor receives a break signal, it drives the ptb0 pin high for the duration of two bits before echoing the break signal. figure 9-6. break transaction 9.4.6 commands the monitor rom uses the following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 116 monitor rom (mon) motorola table 9-4. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result table 9-5. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola monitor rom (mon) 117 note: a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64-kbyte memory map. table 9-6. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence data iread iread data echo sent to monitor result table 9-7. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iwrite iwrite data echo sent to monitor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 118 monitor rom (mon) motorola table 9-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence sp high readsp readsp sp low echo sent to monitor result table 9-9. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) security mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola monitor rom (mon) 119 9.5 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user- defined data. note: do not leave locations $fff6?$fffd blank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin ptb0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 9-7 .) figure 9-7. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo ptb0 rst v dd 4096 + 32 oscxclk cycles 24 bus cycles 141 12 1 break notes: 2 = data return delay, 2 bit times 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 120 monitor rom (mon) motorola upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note: the mcu does not transmit a break character until after the host sends the eight security bytes. to determine whether the security code entered is correct, check to see if bit 6 of ram address $40 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the security sequence, the flash module can also be mass erased by executing an erase routine that was downloaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 121 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 10. timer interface module (tim) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 10.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 10.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 10.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 126 10.5.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . .127 10.5.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . .127 10.5.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . 128 10.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . .129 10.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 10.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 10.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 10.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . .134 10.10.2 tim counter registers (tcnth:tcntl) . . . . . . . . . . . . . . 136 10.10.3 tim counter modulo registers (tmodh:tmodl) . . . . . . 137 10.10.4 tim channel status and control registers (tsc0:tsc1) .138 10.10.5 tim channel registers (tch0h/l:tch1h/l) . . . . . . . . . . 142 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 122 timer interface module (tim) motorola 10.2 introduction this section describes the timer interface module (tim2, version b). the tim is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 10-1 is a block diagram of the tim. 10.3 features features of the tim include the following: two input capture/output compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input with 7-frequency internal bus clock prescaler selection free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits 10.4 pin name conventions the tim share two i/o pins with two port d i/o pins. the full name of the tim i/o pins are listed in table 10-1 . the generic pin name appear in the text that follows. table 10-1. pin name conventions tim generic pin names: tch0 tch1 full tim pin names: ptd4/tch0 ptd5/tch1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 123 10.5 functional description figure 10-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels are programmable independently as input capture or output compare channels. figure 10-1. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock tch1 tch0 interrupt logic port logic interrupt logic interrupt logic port logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 124 timer interface module (tim) motorola addr. register name bit 7654321bit 0 $0020 tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $0022 tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $0024 tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0025 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0027 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0028 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 10-2. tim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 125 10.5.1 tim counter prescaler the tim clock source is one of the seven prescaler outputs. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc) select the tim clock source. 10.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 10.5.3 output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0029 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $002a tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset = unimplemented figure 10-2. tim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 126 timer interface module (tim) motorola 10.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 127 10.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 10.5.4 pulse width modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 10-3 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic one. program the tim to set the pin if the state of the pwm pulse is logic zero. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 128 timer interface module (tim) motorola figure 10-3. pwm period and pulse width the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is 000 (see 10.10.1 tim status and control register (tsc) ). the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 10.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 10.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. tchx period pulse width overflow overflow overflow output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 129 use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 10.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 130 timer interface module (tim) motorola note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 10.5.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. (see table 10-3 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 10-3 .) note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) interrupts mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 131 setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim status control register 0 (tsc0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 10.10.4 tim channel status and control registers (tsc0:tsc1) .) 10.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie=1. chxf and chxie are in the tim channel x status and control register. 10.7 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 132 timer interface module (tim) motorola 10.7.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. 10.7.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 10.8 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whether status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see 7.8.3 break flag control register (bfcr) .) to allow software to clear status bits during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o signals mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 133 10.9 i/o signals port d shares two of its pins with the tim. the two tim channel i/o pins are ptd4/tch0 and ptd5/tch1. each channel i/o pin is programmable independently as an input capture pin or an output compare pin. ptd4/tch0 can be configured as a buffered output compare or buffered pwm pin. 10.10 i/o registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0 and tsc1) tim channel registers (tch0h:tch0l and tch1h:tch1l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 134 timer interface module (tim) motorola 10.10.1 tim status and control register (tsc) the tim status and control register does the following: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic zero to tof. if another tim overflow occurs before the clearing sequence is complete, then writing logic zero to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic one to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 10-4. tim status and control register (tsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 135 tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as logic zero. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 10-2 shows. reset clears the ps[2:0] bits. table 10-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 not available f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 136 timer interface module (tim) motorola 10.10.2 tim counter registers (tcnth:tcntl) the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. address: $0021 tcnth bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 address: $0022 tcntl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 = unimplemented figure 10-5. tim counter registers (tcnth:tcntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 137 10.10.3 tim counter modulo registers (tmodh:tmodl) the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. address: $0023 tmodh bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 address: $0024 tmodl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 figure 10-6. tim counter modulo registers (tmodh:tmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 138 timer interface module (tim) motorola 10.10.4 tim channel status and control registers (tsc0:tsc1) each of the tim channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation address: $0025 tsc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0028 tsc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 10-7. tim channel status and control registers (tsc0:tsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 139 chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chxie=1), clear chxf by reading the tim channel x status and control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa 0:0, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 10-3 . 1 = unbuffered output compare/pwm operation 0 = input capture operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 140 timer interface module (tim) motorola when elsxb:elsxa = 0:0, this read/write bit selects the initial output level of the tchx pin. (see table 10-3 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 10-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 10-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola timer interface module (tim) 141 note: before enabling a tim channel register for input capture operation, make sure that the tchx pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at logic one, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 10-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 10-8. chxmax latency output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 142 timer interface module (tim) motorola 10.10.5 tim channel registers (tch0h/l:tch1h/l) these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading the high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x registers (tchxh) inhibits output compares until the low byte (tchxl) is written. address: $0026 tch0h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0027 tch0l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset address: $0029 tch1h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $02a tch1l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset figure 10-9. tim channel registers (tch0h/l:tch1h/l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 143 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 11. analog-to-digital converter (adc) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 11.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 11.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.7.1 adc voltage in (adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 11.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . . 148 11.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.2 introduction this section describes the 12-channel, 8-bit linear successive approximation analog-to-digital converter (adc). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 144 analog-to-digital converter (adc) motorola 11.3 features features of the adc module include: 12 channels with multiplexed input linear successive approximation with monotonicity 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt selectable adc clock 11.4 functional description twelve adc channels are available for sampling external sources at pins ptb0?ptb7 and ptd0?ptd3. an analog multiplexer allows the single adc converter to select one of the 12 adc channels as adc voltage input (adcvin). adcvin is converted by the successive approximation register-based counters. the adc resolution is 8 bits. when the conversion is completed, adc puts the result in the adc data register and sets a flag or generates an interrupt. figure 11-2 shows a block diagram of the adc. addr.register name bit 7654321bit 0 $003c adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset $003e adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 figure 11-1. adc i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 145 figure 11-2. adc block diagram 11.4.1 adc port i/o pins ptb0?ptb7 and ptd0?ptd3 are general-purpose i/o pins that are shared with the adc channels. the channel select bits (adc status and control register, $003c), define which adc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and can be used as general-purpose i/o. internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable adc channel x read ddrb/ddrd write ddrb/ddrd reset write ptb/ptd read ptb/ptd ddrbx/ddrdx ptbx/ptdx (1 of 12 channels) adcx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 146 analog-to-digital converter (adc) motorola writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a logic 0 if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. 11.4.2 voltage conversion when the input voltage to the adc equals v dd , the adc converts the signal to $ff (full scale). if the input voltage equals v ss , the adc converts it to $00. input voltages between v dd and v ss are a straight-line linear conversion. all other input voltages will result in $ff if greater than v dd and $00 if less than v ss . note: input voltage should not exceed the analog supply voltages. 11.4.3 conversion time fourteen adc internal clocks are required to perform one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immediately following a write to the adscr. if the adc internal clock is selected to run at 1mhz, then one conversion will take 14 s to complete. with a 1mhz adc internal clock the maximum sample rate is 71.43khz. 11.4.4 continuous conversion in the continuous conversion mode, the adc continuously converts the selected channel filling the adc data register with new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not. conversions will continue until the adco bit is cleared. the coco bit (adc status and control register, $003c) is set after each conversion and can be cleared by writing the adc status and control register or reading of the adc data register. 14 adc clock cycles conversion time = adc clock frequency number of bus cycles = conversion time bus frequency f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) interrupts mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 147 11.4.5 accuracy and precision the conversion process is monotonic and has no missing codes. 11.5 interrupts when the aien bit is set, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 11.6 low-power modes the following subsections describe the adc in low-power modes. 11.6.1 wait mode the adc continues normal operation during wait mode. any enabled cpu interrupt request from the adc can bring the mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by setting the adch[4:0] bits in the adc status and control register to logic 1?s before executing the wait instruction. 11.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before attempting a new adc conversion after exiting stop mode. 11.7 i/o signals the adc module has 12 channels that are shared with i/o port b and port d. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 148 analog-to-digital converter (adc) motorola 11.7.1 adc voltage in (adcvin) adcvin is the input voltage signal from one of the 12 adc channels to the adc module. 11.8 i/o registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adr) adc clock register (adiclk) 11.8.1 adc status and control register the following paragraphs describe the function of the adc status and control register. coco ? conversions complete bit when the aien bit is a logic 0, the coco is a read-only bit which is set each time a conversion is completed. this bit is cleared whenever the adc status and control register is written or whenever the adc data register is read. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) when the aien bit is a logic 1 (cpu interrupt enabled), the coco is a read-only bit, and will always be logic 0 when read. address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 11-3. adc status and control register (adscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 149 aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the adc channels. the five channel select bits are detailed in the following table. care should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. (see table 11-1.) the adc subsystem is turned off when the channel select bits are all set to one. this feature allows for reduced power consumption for the mcu when the adc is not used. reset sets all of these bits to a logic 1. note: recovery from the disabled state requires one conversion cycle to stabilize. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 150 analog-to-digital converter (adc) motorola table 11-1. mux channel select adch4 adch3 adch2 adch1 adch0 adc channel input select 00000adc0 ptb0 00001adc1 ptb1 00010adc2 ptb2 00011adc3 ptb3 00100adc4 ptb4 00101adc5 ptb5 00110adc6 ptb6 00111adc7 ptb7 01000adc8 ptd3 01001adc9 ptd2 01010adc10 ptd1 01011adc11 ptd0 01100 unused (see note 1) ::::: ? 11010 11011 ? reserved 11 1 0 0 ? unused 11 1 0 1 v dda (see note 2) 11 1 1 0 v ssa (see note 2) 11 1 1 1 adc power off notes: 1. if any unused channels are selected, the resulting adc conversion will be unknown. 2. the voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the adc converter both in production test and for user applications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) i/o registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola analog-to-digital converter (adc) 151 11.8.2 adc data register one 8-bit result register is provided. this register is updated each time an adc conversion completes. 11.8.3 adc input clock register this register selects the clock frequency for the adc. adiv[2:0] ? adc clock prescaler bits adiv[2:0] form a 3-bit field which selects the divide ratio used by the adc to generate the internal adc clock. table 11-2 shows the available clock configurations. the adc clock should be set to approximately 1mhz. address: $003d bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 11-4. adc data register (adr) address: $003e bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset: 0 0000000 = unimplemented figure 11-5. adc input clock register (adiclk) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . analog-to-digital converter (adc) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 152 analog-to-digital converter (adc) motorola table 11-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola input/output (i/o) ports 153 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 12. input/output (i/o) ports 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 12.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 156 12.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 157 12.3.3 port a input pull-up enable register (ptapue) . . . . . . . . 158 12.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 159 12.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 160 12.5 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 12.5.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 162 12.5.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 163 12.5.3 port d control register (pdcr). . . . . . . . . . . . . . . . . . . . . 164 12.2 introduction twenty three (23) bidirectional input-output (i/o) pins form three parallel ports. all i/o pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 154 input/output (i/o) ports motorola addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $000a port d control register (pdcr) read: 0000 slowd7 slowd6 ptdpu7 ptdpu6 write: reset:00000000 $000d port a input pull-up enable register (ptapue) read: pta6en ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 figure 12-1. i/o port register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports introduction mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola input/output (i/o) ports 155 table 12-1. port control register bits summary port bit ddr module control pin module register control bit a 0 ddra0 kbi kbier ($001b) kbie0 pta0/kbi0 1 ddra1 kbie1 pta1/kbi1 2 ddra2 kbie2 pta2/kbi2 3 ddra3 kbie3 pta3/kbi3 4 ddra4 kbie4 pta4/kbi4 5 ddra5 kbie5 pta5/kbi5 6 ddra6 osc kbi ptapue ($000d) kbier ($001b) pta6en kbie6 rcclk/pta6/kbi6 (1) b 0 ddrb0 adc adscr ($003c) adch[4:0] ptb0/adc0 1 ddrb1 ptb1/adc1 2 ddrb2 ptb2/adc2 3 ddrb3 ptb3/adc3 4 ddrb4 ptb4/adc4 5 ddrb5 ptb5/adc5 6 ddrb6 ptb6/adc6 7 ddrb7 ptb7/adc7 d 0 ddrd0 adc adscr ($003c) adch[4:0] ptd0/adc11 1 ddrd1 ptd1/adc10 2 ddrd2 ptd2/adc9 3 ddrd3 ptd3/adc8 4 ddrd4 tim tsc0 ($0025) els0b:els0a ptd4/tch0 5 ddrd5 tsc1 ($0028) els1b:els1a ptd5/tch1 6 ddrd6 ? ? ? ptd6 7 ddrd7 ? ? ? ptd7 notes : 1. rcclk/pta6/kbi6 pin is only available on mc68hrc908jl3e/jk3e/jk1e devices (rc option); ptapue register has priority control over the port pin. rcclk/pta6/kbi6 is the osc2 pin on mc68hc908jl3e/jk3e/jk1e devices (x-tal option). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 156 input/output (i/o) ports motorola 12.3 port a port a is an 7-bit special function port that shares all seven of its pins with the keyboard interrupt (kbi) module (see section 14. keyboard interrupt module (kbi) ). each port a pin also has software configurable pull-up device if the corresponding port pin is configured as input port. pta0 to pta5 has direct led drive capability. note: pta0?pta5 pins are available on mc68h(r)c908jl3e only. pta6 pin is available on mc68hrc908jl3e/jk3e/jk1e only. 12.3.1 port a data register (pta) the port a data register (pta) contains a data latch for each of the seven port a pins. pta[6:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. kbi[6:0] ? port a keyboard interrupts the keyboard interrupt enable bits, kbie[6:0], in the keyboard interrupt control register (kbier) enable the port a pins as external interrupt pins, (see section 14. keyboard interrupt module (kbi) ). address: $0000 bit 7654321bit 0 read: 0 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset additional functions: led (sink) led (sink) led (sink) led (sink) led (sink) led (sink) 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up 30k pull-up keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt figure 12-2. port a data register (pta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port a mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola input/output (i/o) ports 157 12.3.2 data direction register a (ddra) data direction register a determines whether each port a pin is an input or an output. writing a logic one to a ddra bit enables the output buffer for the corresponding port a pin; a logic zero disables the output buffer. ddra[6:0] ? data direction register a bits these read/write bits control port a data direction. reset clears ddra[6:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 12-4 shows the port a i/o logic. figure 12-4. port a i/o circuit address: $0004 bit 7654321bit 0 read: 0 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 12-3. data direction register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus 30k ptapuex to keyboard interrupt circuit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 158 input/output (i/o) ports motorola when ddrax is a logic 1, reading address $0000 reads the ptax data latch. when ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. 12.3.3 port a input pull-up enable register (ptapue) the port a input pull-up enable register (ptapue) contains a software configurable pull-up device for each of the seven port a pins. each bit is individually configurable and requires the corresponding data direction register, ddrax be configured as input. each pull-up device is automatically and dynamically disabled when its corresponding ddrax bit is configured as output. pta6en ? enable pta6 on osc2 this read/write bit configures the osc2 pin function when rc oscillator option is selected. this bit has no effect for x-tal oscillator option. 1 = osc2 pin configured for pta6 i/o, and has all the interrupt and pull-up functions 0 = osc2 pin outputs the rc oscillator clock (rcclk) ptapue[6:0] ? port a input pull-up enable bits these read/write bits are software programmable to enable pull-up devices on port a pins 1 = corresponding port a pin configured to have internal pull-up if its ddra bit is set to 0 0 = pull-up device is disconnected on the corresponding port a pin regardless of the state of its ddra bit address: $000d bit 7654321bit 0 read: pta6en ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 figure 12-5. port a input pull-up enable register (ptapue) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola input/output (i/o) ports 159 table 12-2 summarizes the operation of the port a pins. 12.4 port b port b is an 8-bit special function port that shares all eight of its port pins with the analog-to-digital converter (adc) module, see section 11. 12.4.1 port b data register (ptb) the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. table 12-2. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10x (1) input, v dd (2) ddra[6:0] pin pta[6:0] (3) 0 0 x input, hi-z (4) ddra[6:0] pin pta[6:0] (3) x 1 x output ddra[6:0] pta[6:0] pta[6:0] notes : 1. x = don?t care. 2. i/o pin pulled to v dd by internal pull-up. 3. writing affects data register, but does not affect input. 4. hi-z = high impedance. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: adc7 adc6 adc5 adc4 adc3 adc2 adc2 adc0 figure 12-6. port b data register (ptb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 160 input/output (i/o) ports motorola adc[7:0] ? adc channels 7 to 0 adc[7:0] are pins used for the input channels to the analog-to-digital converter module. the channel select bits, adch[4:0], in the adc status and control register define which port pin will be used as an adc input and overrides any control from the port i/o logic. see section 11. analog-to-digital converter (adc) . 12.4.2 data direction register b (ddrb) data direction register b determines whether each port b pin is an input or an output. writing a logic one to a ddrb bit enables the output buffer for the corresponding port b pin; a logic zero disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 12-8 shows the port b i/o logic. address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 12-7. data direction register b (ddrb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola input/output (i/o) ports 161 figure 12-8. port b i/o circuit when ddrbx is a logic 1, reading address $0001 reads the ptbx data latch. when ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-3 summarizes the operation of the port b pins. 12.5 port d port d is an 8-bit special function port that shares two of its pins with timer interface module, (see section 10. ) and shares four of its pins with analog-to-digital converter module (see section 11. ). ptd6 and ptd7 each has high current drive (25ma sink) and programmable pull-up. ptd2, ptd3, ptd6 and ptd7 each has led driving (sink) capability. note: ptd0?ptd1 are available on mc68h(r)c908jl3e only. table 12-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrb[7:0] pin ptb[7:0] read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus to analog-to-digital converter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 162 input/output (i/o) ports motorola 12.5.1 port d data register (ptd) the port d data register contains a data latch for each of the eight port d pins. ptd[7:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. adc[11:8] ? adc channels 11 to 8 adc[11:8] are pins used for the input channels to the analog-to-digital converter module. the channel select bits, adch[4:0], in the adc status and control register define which port pin will be used as an adc input and overrides any control from the port i/o logic. see section 11. analog-to-digital converter (adc) . tch[1:0] ? timer channel i/o the tch1 and tch0 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptd4/tch0 and ptd5/tch1 pins are timer channel i/o pins or general-purpose i/o pins. see section 10. timer interface module (tim) . address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset additional functions led (sink) led (sink) led (sink) led (sink) adc8 adc9 adc10 adc11 tch1 tch0 25ma sink (slow edge) 25ma sink (slow edge) 5k pull-up 5k pull-up figure 12-9. port d data register (ptd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola input/output (i/o) ports 163 12.5.2 data direction register d (ddrd) data direction register d determines whether each port d pin is an input or an output. writing a logic one to a ddrd bit enables the output buffer for the corresponding port d pin; a logic zero disables the output buffer. ddrd[7:0] ? data direction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writing to the port d data register before changing data direction register d bits from 0 to 1. figure 12-11 shows the port d i/o logic. figure 12-11. port d i/o circuit address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 12-10. data direction register d (ddrd) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus ptd[0:3] to analog-to-digital converter 5k ptdpu[6:7] ptd[4:5] to timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 164 input/output (i/o) ports motorola when ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-4 summarizes the operation of the port d pins. 12.5.3 port d control register (pdcr) the port d control register enables/disables the pull-up resistor and slow-edge high current capability of pins ptd6 and ptd7. slowdx ? slow edge enable the slowd6 and slowd7 bits enable the slow-edge, open-drain, high current output (25ma sink) of port pins ptd6 and ptd7 respectively. ddrdx bit is not affected by slowdx. 1 = slow edge enabled; pin is open-drain output 0 = slow edge disabled; pin is push-pull ptdpux ? pull-up enable the ptdpu6 and ptdpu7 bits enable the 5k ? pull-up on ptd6 and ptd7 respectively, regardless the status of ddrdx bit. 1 = enable 5k ? pull-up 0 = disable 5k ? pull-up table 12-4. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] pin ptd[7:0] address: $000a bit 7654321bit 0 read: 0 0 0 0 slowd7 slowd6 ptdpu7 ptdpu6 write: reset:00000000 figure 12-12. port d control register (pdcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola external interrupt (irq) 165 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 13. external interrupt (irq) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 13.4.1 irq1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . .169 13.6 irq status and control register (intscr) . . . . . . . . . . . . . . 169 13.2 introduction the irq (external interrupt) module provides a maskable interrupt input. 13.3 features features of the irq module include the following: a dedicated external interrupt pin, i rq1 irq1 interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge selectable internal pullup resistor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 166 external interrupt (irq) motorola 13.4 functional description a logic zero applied to the external interrupt pin can latch a cpu interrupt request. figure 13-1 shows the structure of the irq module. interrupt signals on the irq1 pin are latched into the irq1 latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (intscr). writing a logic one to the ack1 bit clears the irq1 latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered and is software- configurable to be either falling-edge or falling-edge and low-level- triggered. the mode1 bit in the intscr controls the triggering sensitivity of the irq1 pin. when the interrupt pin is edge-triggered only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both falling-edge and low-level-triggered, the cpu interrupt request remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic one the vector fetch or software clear may occur before or after the interrupt pin returns to logic one. as long as the pin is low, the interrupt request remains pending. a reset will clear the latch and the mode1 control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask1 bit in the intscr mask all external interrupt requests. a latched interrupt request is not presented to the interrupt priority logic unless the imask1 bit is clear. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola external interrupt (irq) 167 note: the interrupt mask (i) in the condition code register (ccr) masks all interrupt requests, including external interrupt requests. (see 7.6 exception control .) figure 13-1. irq module block diagram 13.4.1 irq1 pin a logic zero on the irq1 pin can latch an interrupt request into the irq1 latch. a vector fetch, software clear, or reset clears the irq1 latch. if the mode1 bit is set, the irq1 pin is both falling-edge-sensitive and low-level-sensitive. with mode1 set, both of the following actions must occur to clear irq1: ack1 imask1 dq ck clr irq1 high interrupt to mode select logic irq1 ff request v dd mode1 voltage detect synchro- nizer irqf1 to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device irq1 irqpud addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) read: 0000irqf10 imask1 mode1 write: ack1 reset:00000000 = unimplemented figure 13-2. irq i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 168 external interrupt (irq) motorola vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt acknowledge signal by writing a logic one to the ack1 bit in the interrupt status and control register (intscr). the ack1 bit is useful in applications that poll the irq1 pin and require software to clear the irq1 latch. writing to the ack1 bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ack1 does not affect subsequent transitions on the irq1 pin. a falling edge that occurs after writing to the ack1 bit latches another interrupt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq1 pin to logic one ? as long as the irq1 pin is at logic zero, irq1 remains active. the vector fetch or software clear and the return of the irq1 pin to logic one may occur in any order. the interrupt request remains pending as long as the irq1 pin is at logic zero. a reset will clear the latch and the mode1 control bit, thereby clearing the interrupt even if the pin stays low. if the mode1 bit is clear, the irq1 pin is falling-edge-sensitive only. with mode1 clear, a vector fetch or software clear immediately clears the irq1 latch. the irqf1 bit in the intscr register can be used to check for pending interrupts. the irqf1 bit is not affected by the imask1 bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq1 pin. note: when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. note: an internal pull-up resistor to v dd is connected to the irq1 pin; this can be disabled by setting the irqpud bit in the config2 register ($001e). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq module during break interrupts mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola external interrupt (irq) 169 13.5 irq module during break interrupts the system integration module (sim) controls whether the irq1 latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 7. system integration module (sim) .) to allow software to clear the irq1 latch during a break interrupt, write a logic one to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), writing to the ack1 bit in the irq status and control register during the break state has no effect on the irq latch. 13.6 irq status and control register (intscr) the irq status and control register (intscr) controls and monitors operation of the irq module. the intscr has the following functions: shows the state of the irq1 flag clears the irq1 latch masks irq1 and interrupt request controls triggering sensitivity of the irq1 interrupt pin address: $001d bit 7654321bit 0 read: 0000irqf1 imask1 mode1 write: ack1 reset:00000000 = unimplemented figure 13-3. irq status and control register (intscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 170 external interrupt (irq) motorola irqf1 ? irq1 flag this read-only status bit is high when the irq1 interrupt is pending. 1 = irq1 interrupt pending 0 = irq1 interrupt not pending ack1 ? irq1 interrupt request acknowledge bit writing a logic one to this write-only bit clears the irq1 latch. ack1 always reads as logic zero. reset clears ack1. imask1 ? irq1 interrupt mask bit writing a logic one to this read/write bit disables irq1 interrupt requests. reset clears imask1. 1 = irq1 interrupt requests disabled 0 = irq1 interrupt requests enabled mode1 ? irq1 edge/level select bit this read/write bit controls the triggering sensitivity of the irq1 pin. reset clears mode1. 1 = irq1 interrupt requests on falling edges and low levels 0 = irq1 interrupt requests on falling edges only irqpud ? irq1 pin pull-up control bit 1 = internal pull-up is disconnected 0 = internal pull-up is connected between irq1 pin and v dd address: $001e bit 7654321bit 0 read: irqpudrrlvit1lvit0rrr write: reset:000 not affected not affected 000 por:00000000 r=reserved figure 13-4. configuration register 2 (config2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola keyboard interrupt module (kbi) 171 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 14. keyboard interrupt module (kbi) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 14.4.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.4.2 keyboard status and control register. . . . . . . . . . . . . . . . 175 14.4.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 176 14.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 14.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 14.6 keyboard module during break interrupts . . . . . . . . . . . . . . .177 14.2 introduction the keyboard interrupt module (kbi) provides seven independently maskable external interrupts which are accessible via pta0?pta6 pins. 14.3 features features of the keyboard interrupt module include the following: seven keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask software configurable pull-up device if input pin is configured as input port bit programmable edge-only or edge- and level- interrupt sensitivity exit from low-power modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 172 keyboard interrupt module (kbi) motorola 14.4 functional description figure 14-2. keyboard interrupt block diagram writing to the kbie6?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin in port a also enables its internal pull-up device irrespective of ptapuex bits in the port a input pull-up enable register (see 12.3.3 port a input pull-up enable register (ptapue) ). a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. addr.register name bit 7654321bit 0 $001a keyboard status and control register (kbscr) read: 0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 14-1. kbi i/o register summary kbie0 kbie6 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi6 kbi0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola keyboard interrupt module (kbi) 173 a keyboard interrupt is latched when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the interrupt acknowledge signal by writing a logic 1 to the ackk bit in the keyboard status and control register kbscr. the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interrupt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 174 keyboard interrupt module (kbi) motorola if the modek bit is clear, the keyboard interrupt pin is falling-edge- sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, disable the pull- up device, use the data direction register to configure the pin as an input and then read the data register. note: setting a keyboard interrupt enable bit (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. 14.4.1 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. therefore a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. an interrupt signal on an edge- and f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola keyboard interrupt module (kbi) 175 level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in the data direction register a. 2. write logic 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 14.4.2 keyboard status and control register flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity bits 7?4 ? not used these read-only bits always read as logic 0?s. keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port- a. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending address: $001a bit 7654321bit 0 read: 0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 14-3. keyboard status and control register (kbscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 176 keyboard interrupt module (kbi) motorola ackk ? keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-a. ackk always reads as logic 0. reset clears ackk. imaskk? keyboard interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port-a. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port-a. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 14.4.3 keyboard interrupt enable register the port-a keyboard interrupt enable register enables or disables each port-a pin to operate as a keyboard interrupt pin. kbie6?kbie0 ? port-a keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin on port-a to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbix pin enabled as keyboard interrupt pin 0 = kbix pin not enabled as keyboard interrupt pin address: $001b bit 7654321bit 0 read: 0 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 14-4. keyboard interrupt enable register (kbier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) low-power modes mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola keyboard interrupt module (kbi) 177 14.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 14.5.1 wait mode the keyboard modules remain active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 14.5.2 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 14.6 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 178 keyboard interrupt module (kbi) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola computer operating properly (cop) 179 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 15. computer operating properly (cop) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.1 2oscout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 15.4.5 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 15.4.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 15.4.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . 182 15.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 15.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 15.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . .184 15.2 introduction the computer operating properly (cop) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config1 register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 180 computer operating properly (cop) motorola 15.3 functional description figure 15-1 shows the structure of the cop module. figure 15-1. cop block diagram the cop counter is a free-running 6-bit counter preceded by the 12-bit system integration module (sim) counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 2oscout cycles; depending on the state of the cop rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 2oscout cycle overflow option, a 8mhz crystal gives a cop timeout period of 32.766 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the sim counter. copctl write 2oscout reset vector fetch sim reset circuit reset status register internal reset sources (1) sim clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop counter note: 1. see sim section for more details. cop clock cop timeout cop rate sel (coprs from config1) 6-bit cop counter f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) i/o signals mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola computer operating properly (cop) 181 note: service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 2oscout cycles and sets the cop bit in the reset status register (rsr). (see 7.8.2 reset status register (rsr) .). note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subroutine could keep the cop from generating a reset even while the main program is not working properly. 15.4 i/o signals the following paragraphs describe the signals shown in figure 15-1 . 15.4.1 2oscout 2oscout is the oscillator output signal. 2oscout frequency is equal to the crystal frequency or the rc-oscillator frequency. 15.4.2 copctl write writing any value to the cop control register (copctl) (see 15.5 cop control register ) clears the cop counter and clears bits 12 through 5 of the sim counter. reading the cop control register returns the low byte of the reset vector. 15.4.3 power-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 2oscout cycles after power-up. 15.4.4 internal reset an internal reset clears the sim counter and the cop counter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 182 computer operating properly (cop) motorola 15.4.5 reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the sim counter. 15.4.6 copd (cop disable) the copd signal reflects the state of the cop disable bit (copd) in the configuration register (config). (see section 5. configuration register (config) .) 15.4.7 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register 1. coprs ? cop rate select bit coprs selects the cop timeout period. reset clears coprs. 1 = cop timeout period is (2 13 ? 2 4 ) 2oscout cycles 0 = cop timeout period is (2 18 ? 2 4 ) 2oscout cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: coprsr rlvidrssrecstopcopd write: reset:00000000 r=reserved figure 15-2. configuration register 1 (config1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola computer operating properly (cop) 183 15.5 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 15.6 interrupts the cop does not generate cpu interrupt requests. 15.7 monitor mode the cop is disabled in monitor mode when v dd +v hi is present on the irq1 pin or on the rst pin. 15.8 low-power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 15.8.1 wait mode the cop continues to operate during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 15-3. cop control register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 184 computer operating properly (cop) motorola 15.8.2 stop mode stop mode turns off the 2oscout input to the cop and clears the sim counter. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. 15.9 cop module during break mode the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola low voltage inhibit (lvi) 185 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 16. low voltage inhibit (lvi) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 16.5 lvi control register (config2/config1) . . . . . . . . . . . . . . 186 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 16.2 introduction this section describes the low-voltage inhibit module (lvi), which monitors the voltage on the v dd pin and generates a reset when the v dd voltage falls to the lvi trip (lvi trip ) voltage. 16.3 features features of the lvi module include the following: selectable lvi trip voltage selectable lvi circuit disable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low voltage inhibit (lvi) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 186 low voltage inhibit (lvi) motorola 16.4 functional description figure 16-1 shows the structure of the lvi module. the lvi is enabled after a reset. the lvi module contains a bandgap reference circuit and comparator. setting lvi disable bit (lvid) disables the lvi to monitor v dd voltage. the lvi trip voltage selection bits (lvit1, lvit0) determine at which v dd level the lvi module should take actions. the lvi module generates one output signal: lvi reset ? an reset signal will be generated to reset the cpu when v dd drops to below the set trip point. figure 16-1. lvi module block diagram 16.5 lvi control register (config2/config1) low v dd lv i t1 lv i d detector v dd lvi reset lv i t 0 v dd > lvi trip = 0 v dd < lvi trip = 1 address: $001e bit 7654321bit 0 read: irqpudrrlvit1lvit0rrr write: reset:000 not affected not affected 000 por:00000000 r= reserved figure 16-2. configuration register 2 (config2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low voltage inhibit (lvi) low-power modes mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola low voltage inhibit (lvi) 187 lvid ? low voltage inhibit disable bit 1 = low voltage inhibit disabled 0 = low voltage inhibit enabled lvit1, lvit0 ? lvi trip voltage selection these two bits determine at which level of v dd the lvi module will come into action. lvit1 and lvit0 are cleared by a power-on reset only. 16.6 low-power modes the stop and wait instructions put the mcu in low-power- consumption standby modes. 16.6.1 wait mode the lvi module, when enabled, will continue to operate in wait mode. 16.6.2 stop mode the lvi module, when enabled, will continue to operate in stop mode. address: $001f bit 7654321bit 0 read: coprs r r lvid r ssrec stop copd write: reset:00000000 r=reserved figure 16-3. configuration register 1 (config1) lvit1 lvit0 trip voltage (1) 1. see section 18. electrical specifications for full parameters. comments 00v lv r 3 (2.4v) for v dd =3v operation 01v lv r 3 (2.4v) for v dd =3v operation 10v lv r 5 (4.0v) for v dd =5v operation 11reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low voltage inhibit (lvi) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 188 low voltage inhibit (lvi) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola break module (break) 189 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 17. break module (break) 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 17.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.4.1 flag protection during break interrupts . . . . . . . . . . . . . . .192 17.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 192 17.4.3 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . 192 17.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 192 17.5 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 17.5.1 break status and control register (brkscr) . . . . . . . . . 193 17.5.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . .194 17.5.3 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 17.5.4 break flag control register (bfcr) . . . . . . . . . . . . . . . . . 196 17.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 17.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 17.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 17.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 190 break module (break) motorola 17.3 features features of the break module include the following: accessible i/o registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 17.4 functional description when the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (bkpt ) to the sim. the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a logic one to the brka bit in the break status and control register. when a cpu generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return from interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 17-1 shows the structure of the break module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) functional description mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola break module (break) 191 figure 17-1. break module block diagram iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt (to sim) addr.register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 17-2. break i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 192 break module (break) motorola 17.4.1 flag protection during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see 7.8.3 break flag control register (bfcr) and see the break interrupts subsection for each module.) 17.4.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd ($fefc:$fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 17.4.3 tim during break interrupts a break interrupt stops the timer counter. 17.4.4 cop during break interrupts the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. 17.5 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) break status register (bsr) break flag control register (bfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) break module registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola break module (break) 193 17.5.1 break status and control register (brkscr) the break status and control register contains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a logic zero to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a logic one to brka generates a break interrupt. clear brka by writing a logic zero to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 17-3. break status and control register (brkscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 194 break module (break) motorola 17.5.2 break address registers the break address registers contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. 17.5.3 break status register the break status register contains a flag to indicate that a break caused an exit from stop or wait mode. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 17-4. break address register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 17-5. break address register low (brkl) address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a logic zero clears sbsw. figure 17-6. break status register (bsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) break module registers mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola break module (break) 195 sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic zero to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi routine. the user can modify the return address on the stack by subtracting one from it. the following code is an example of this. ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (break) technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 196 break module (break) motorola 17.5.4 break flag control register (bfcr) the break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break 17.6 low-power modes the wait and stop instructions put the mcu in low-power- consumption standby modes. 17.6.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the return address on the stack if sbsw is set (see 7.7 low-power modes ). clear the sbsw bit by writing logic zero to it. 17.6.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. see 7.8 sim registers . address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 17-7. break flag control register (bfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola electrical specifications 197 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 18. electrical specifications 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 18.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . .198 18.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 199 18.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 18.6 5v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 200 18.7 5v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 18.8 5v oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 202 18.9 3v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . 203 18.10 3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 18.11 3v oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 205 18.12 typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 18.13 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 18.14 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 18.2 introduction this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 198 electrical specifications motorola 18.3 absolute maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. note: this device is not guaranteed to operate properly at the maximum ratings. refer to sections 18.6 and 18.9 for guaranteed operating conditions. note: this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) table 18-1. absolute maximum ratings characteristic (1) notes: 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v mode entry voltage, i rq1 pin v dd +v hi v ss ?0.3 to +8.5 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications functional operating range mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola electrical specifications 199 18.4 functional operating range 18.5 thermal characteristics table 18-2. operating range characteristic symbol value unit operating temperature range t a ? 40 to +125 ? 40 to +85 c operating voltage range v dd 5 10% 3 10% v table 18-3. thermal characteristics characteristic symbol value unit thermal resistance 20-pin pdip 20-pin soic 28-pin pdip 28-pin soic 48-pin lqfp ja 70 70 70 70 80 c/w c/w c/w c/w c/w i/o pin power dissipation p i/o user determined w power dissipation (1) notes: 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c ) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 200 electrical specifications motorola 18.6 5v dc electrical characteristics table 18-4. dc electrical characteristics (5v) characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0ma) pta0?pta6, ptb0?ptb7, ptd0?ptd7 v oh v dd ?0.8 ??v output low voltage (i load = 1.6ma) pta6, ptb0?ptb7, ptd0, ptd1, ptd4, ptd5 v ol ??0.4v output low voltage (i load = 25ma) ptd6, ptd7 v ol ??0.5v led drives (v ol = 3v) pta0?pta5, ptd2, ptd3, ptd6, ptd7 i ol 10 16 22 ma input high voltage pta0?pta6, ptb0?ptb7, ptd0?ptd7, rst , irq 1 , osc1 v ih 0.7 v dd ? v dd v input low voltage pta0?pta6, ptb0?ptb7, ptd0?ptd7, rst , irq 1 , osc1 v il v ss ? 0.3 v dd v v dd supply current, f op = 4mhz run (3) mc68hc908jl3e/jk3e/jk1e mc68hrc908jl3e/jk3e/jk1e wait (4) mc68hc908jl3e/jk3e/jk1e mc68hrc908jl3e/jk3e/jk1e stop (5) (?40 c to 85 c) mc68hc908jl3e/jk3e/jk1e mc68hrc908jl3e/jk3e/jk1e (? 40 c to 125 c) mc68hc908jl3e/jk3e/jk1e mc68hrc908jl3e/jk3e/jk1e i dd ? ? ? ? ? ? ? ? 10 4.5 6 1 2 2 2 2 11 5 6.5 1.5 5 5 10 10 ma ma ma ma a a a a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (6) v por 0 ? 100 mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd +v hi 1.5 v dd ? 8.5 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 5v control timing mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola electrical specifications 201 18.7 5v control timing pullup resistors (8) ptd6, ptd7 rst , irq1 , pta0?pta6 r pu1 r pu2 1.8 16 3.3 26 4.8 36 k ? k ? lvi r e set vo lta ge v lv r 5 3.6 4.0 4.4 v notes: 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f op = 4mhz). all inputs 0.2v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 4mhz). all inputs 0.2v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with osc1 grounded; no port pins sourcing current. lvi is disabled. 6. maximum is highest voltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0v. table 18-5. control timing (5v) characteristic (1) notes: 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v ss , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. f op ?8mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 750 ? ns table 18-4. dc electrical characteristics (5v) characteristic (1) symbol min typ (2) max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 202 electrical specifications motorola 18.8 5v oscillator characteristics figure 18-1. rc vs. frequency (5v @25 c) table 18-6. oscillator component specifications (5v) characteristic symbol min typ max unit crystal frequency, xtalclk f oscxclk ?10 32 mhz rc oscillator frequency, rcclk f rcclk 210 12 mhz external clock reference frequency (1) notes: 1. no more than 10% duty cycle deviation from 50%. f oscxclk dc ? 32 mhz crystal load capacitance (2) 2. consult crystal vendor data sheet. c l ?? ? crystal fixed capacitance (2) c 1 ? 2 c l ? crystal tuning capacitance (2) c 2 ? 2 c l ? feedback bias resistor r b ? 10 m ? ? series resistor (2), (3) 3. not required for high frequency crystals. r s ?? ? rc oscillator external r r ext see figure 18-1 rc oscillator external c c ext ?10 ? pf r ext c ext osc1 v dd mcu 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ) rc frequency, f rcclk (mhz) c ext = 10 pf 5v @ 25 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3v dc electrical characteristics mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola electrical specifications 203 18.9 3v dc electrical characteristics table 18-7. dc electrical characteristics (3v) characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?1.0ma) pta0?pta6, ptb0?ptb7, ptd0?ptd7 v oh v dd ?0.4 ??v output low voltage (i load = 0.8ma) pta6, ptb0?ptb7, ptd0, ptd1, ptd4, ptd5 v ol ??0.4v output low voltage (i load = 20ma) ptd6, ptd7 v ol ??0.5v led drives (v ol = 1.8v) pta0?pta5, ptd2, ptd3, ptd6, ptd7 i ol 3610ma input high voltage pta0?pta6, ptb0?ptb7, ptd0?ptd7, rst , irq 1 , osc1 v ih 0.7 v dd ? v dd v input low voltage pta0?pta6, ptb0?ptb7, ptd0?ptd7, rst , irq 1 , osc1 v il v ss ? 0.3 v dd v v dd supply current, f op = 2mhz run (3) mc68hc908jl3e/jk3e/jk1e mc68hrc908jl3e/jk3e/jk1e wait (4) mc68hc908jl3e/jk3e/jk1e mc68hrc908jl3e/jk3e/jk1e stop (5) (? 40 c to 85 c) mc68hc908jl3e/jk3e/jk1e mc68hrc908jl3e/jk3e/jk1e i dd ? ? ? ? ? ? 3 1.5 1.5 0.2 1 1 3.5 2 2 0.3 5 5 ma ma ma ma a a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (6) v por 0 ? 100 mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd +v hi 1.5 v dd ?8.5v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 204 electrical specifications motorola 18.10 3v control timing pullup resistors (8) ptd6, ptd7 rst , irq1 , pta0?pta6 r pu1 r pu2 1.8 16 3.3 26 4.8 36 k ? k ? lvi r e set vo lta ge v lv r 3 2.0 2.4 2.69 v notes: 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f op = 2mhz). all inputs 0.2v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f op = 2mhz). all inputs 0.2v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with osc1 grounded; no port pins sourcing current. lvi is disabled. 6. maximum is highest voltage that por is guaranteed. 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. 8. r pu1 and r pu2 are measured at v dd = 5.0v. table 18-8. control timing (3v) characteristic (1) notes: 1. v dd = 2.7 to 3.3 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor- mation. f op ?4mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 1.5 ? s table 18-7. dc electrical characteristics (3v) characteristic (1) symbol min typ (2) max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications 3v oscillator characteristics mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola electrical specifications 205 18.11 3v oscillator characteristics figure 18-2. rc vs. frequency (3v @25 c) table 18-9. oscillator component specifications (3v) characteristic symbol min typ max unit crystal frequency, xtalclk f oscxclk ?8 16mhz rc oscillator frequency, rcclk f rcclk 28 12mhz external clock reference frequency (1) notes: 1. no more than 10% duty cycle deviation from 50%. f oscxclk dc ? 16 mhz crystal load capacitance (2) 2. consult crystal vendor data sheet. c l ?? ? crystal fixed capacitance (2) c 1 ? 2 c l ? crystal tuning capacitance (2) c 2 ? 2 c l ? feedback bias resistor r b ? 10 m ? ? series resistor (2), (3) 3. not required for high frequency crystals. r s ?? ? rc oscillator external r r ext see figure 18-2 rc oscillator external c c ext ?10 ? pf r ext c ext osc1 v dd mcu 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? ) rc frequency , f rcclk (mhz) c ext = 10 pf 3v @ 25 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 206 electrical specifications motorola 18.12 typical supply currents figure 18-3. typical operating i dd (mc68hc908jl3e/jk3e/jk1e), with all modules turned on (25 c) figure 18-4. typical operating i dd (mc68hrc908jl3e/jk3e/jk1e), with all modules turned on (25 c) 0 2 4 6 8 10 12 0123456789 f op or f bus (mhz) i dd (ma) 14 mc68hc908jl3e/jk3e/jk1e 5.5 v 3.3 v 0 2 4 6 8 10 0123456789 f op or f bus (mhz) i dd (ma) mc68hrc908jl3e/jk3e/jk1e 5.5 v 3.3 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications typical supply currents mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola electrical specifications 207 figure 18-5. typical wait mode i dd (mc68hc908jl3e/jk3e/jk1e), with all modules turned off (25 c) figure 18-6. typical wait mode i dd (mc68hrc908jl3e/jk3e/jk1e), with all modules turned off (25 c) 0 2 4 6 8 10 0123456789 f op or f bus (mhz) i dd (ma) mc68hc908jl3e/jk3e/jk1e 5.5 v 3.3 v 0 0.25 0.5 0.75 1 1.25 1.50 1.75 2 01 23 456 78 i dd (ma) f op or f bus (mhz) mc68hrc908jl3e/jk3e/jk1e 5.5 v 3.3 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 208 electrical specifications motorola 18.13 adc characteristics table 18-10. adc characteristics characteristic symbol min max unit comments supply voltage v ddad 2.7 (v dd min) 5.5 (v dd max) v input voltages v adin v ss v dd v resolution b ad 88bits absolute accuracy a ad 0.5 1.5 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v ss v dd v power-up time t adpu 16 t aic cycles conversion time t adc 14 15 t aic cycles sample time (1) notes: 1. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. t ads 5? t aic cycles zero input reading (2) 2. zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. z adi 00 01 hex v in = v ss full-scale reading (3) f adi fe ff hex v in = v dd input capacitance c adi ? (20) 8 pf not tested input leakage (3) port b/port d 3. the external system error caused by input leakage current is approximately equal to the product of r source and input current. ?? 1 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications memory characteristics mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola electrical specifications 209 18.14 memory characteristics table 18-11. memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v flash program bus clock frequency ? 1 ? mhz flash read bus clock frequency f read (1) notes: 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8m hz flash page erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 1?ms flash mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 4?ms flash pgm/erase to hven set up time t nvs 10 ? s flash high-voltage hold time t nvh 5? s flash high-voltage hold time (mass erase) t nvh1 100 ? s flash program hold time t pgs 5? s flash program time t prog 30 40 s flash return to read time t rcv (4) 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1? s flash cumulative program hv period t hv (5) 5. thv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 32) t hv max. ?4 ms flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ?10k?cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ?10k?cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ? 10 ? years f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 210 electrical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola mechanical specifications 211 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 19. mechanical specifications 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 19.3 20-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.4 20-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 19.5 28-pin pdip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.6 28-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 19.7 48-pin lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 19.2 introduction this section gives the dimensions for: 20-pin plastic dual in-line package (case #738) 20-pin small outline integrated circuit package (case #751d) 28-pin plastic dual in-line package (case #710) 28-pin small outline integrated circuit package (case #751f) 48-pin low-profile quad flat pack (case #932) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 212 mechanical specifications motorola 19.3 20-pin pdip figure 19-1. 20-pin pdip (case #738) 19.4 20-pin soic figure 19-2. 20-pin soic (case #751d) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 ?a? seating plane k n f g d 20 pl ?t? m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ? a ? ? b ? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c ? t ? seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 28-pin pdip mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola mechanical specifications 213 19.5 28-pin pdip figure 19-3. 28-pin pdip (case #710) 19.6 28-pin soic figure 19-4. 28-pin soic (case #751f) notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 seating plane 15 14 28 m a b k c n f g d h j l dim min max min max inches millimeters a 36.45 37.21 1.435 1.465 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 0 15 0 15 n 0.51 1.02 0.020 0.040 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. j k f 1 15 14 28 -a- -b- 28x 14x d p s a m 0.010 (0.25) b s t m 0.010 (0.25) b m 26x g -t- seating plane c x 45 r m dim min max min max inches millimeters a 17.80 18.05 0.701 0.711 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m p 10.01 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 0 0 8 8 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 214 mechanical specifications motorola 19.7 48-pin lqfp figure 19-5. 48-pin lqfp (case #932) a a1 z 0.200 ab t ? u 4x z 0.200 ac t ? u 4x b b1 1 12 13 24 25 36 37 48 s1 s v v1 p ae ae t, u, z detail y detail y base metal n j f d t ? u m 0.080 z ac section ae ? ae ad g 0.080 ac m top & bottom l w k aa e c h 0.250 r 9 detail ad notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums t, u, and z to be determined at datum plane ab. 5. dimensions s and v to be determined at seating plane ac. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.350. 8. minimum solder plate thickness shall be 0.0076. 9. exact shape of each corner is optional. t u z ab ac gauge plane dim a min max 7.000 bsc millimeters a1 3.500 bsc b 7.000 bsc b1 3.500 bsc c 1.400 1.600 d 0.170 0.270 e 1.350 1.450 f 0.170 0.230 g 0.500 bsc h 0.050 0.150 j 0.090 0.200 k 0.500 0.700 m 12 ref n 0.090 0.160 p 0.250 bsc l 1 5 r 0.150 0.250 s 9.000 bsc s1 4.500 bsc v 9.000 bsc v1 4.500 bsc w 0.200 ref aa 1.000 ref f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola ordering information 215 technical data ? mc68h(r)c908jl3e/jk3e/jk1e section 20. ordering information 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 20.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 20.2 introduction this section contains ordering numbers for the mc68h(r)c908jl3e, mc68h(r)c908jk3e, and mc68h(r)c908jk1e. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ordering information technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 216 ordering information motorola 20.3 mc order numbers table 20-1. mc order numbers mc order number oscillator type flash memory package mc68hc908jl3ecfa mc68hc908jl3emfa crystal oscillator 4096 bytes 48-pin lqfp mc68hrc98jl3ecfa mc68hrc98jl3emfa rc oscillator mc68hc908jl3ecp mc68hc908jl3emp mc68hc908jl3ecdw mc68hc908jl3emdw crystal oscillator 4096 bytes 28-pin package mc68hrc98jl3ecp mc68hrc98jl3emp mc68hrc98jl3ecdw mc68hrc98jl3emdw rc oscillator mc68hc908jk3ecp mc68hc908jk3emp mc68hc908jk3ecdw mc68hc908jk3emdw crystal oscillator 4096 bytes 20-pin package mc68hrc98jk3ecp mc68hrc98jk3emp mc68hrc98jk3ecdw mc68hrc98jk3emdw rc oscillator mc68hc908jk1ecp mc68hc908jk1emp mc68hc908jk1ecdw mc68hc908jk1emdw crystal oscillator 1536 bytes mc68hrc98jk1ecp mc68hrc98jk1emp mc68hrc98jk1ecdw mc68hrc98jk1emdw rc oscillator notes: c = ? 40 c to +85 c m = ? 40 c to +125 c (available for v dd = 5v only) p = plastic dual in-line package (pdip) dw = small outline integrated circuit package (soic) fa = low-profile quad flat pack (lqfp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola mc68HLC908JL3E/jk3e/jk1e 217 technical data ? mc68h(r)c908jl3e/jk3e/jk1e appendix a. mc68HLC908JL3E/jk3e/jk1e a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 a.3 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a.4 low-voltage inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a.5 oscillator options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a.6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 a.6.1 functional operating range . . . . . . . . . . . . . . . . . . . . . . . 218 a.6.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 219 a.6.3 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 a.6.4 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .220 a.6.5 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 a.6.6 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 a.7 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 a.2 introduction this appendix introduces three devices, that are low-voltage versions of mc68hc908jl3e/jk3e/jk1e: mc68HLC908JL3E mc68hlc908jk3e mc68hlc908jk1e the entire data book apply to these low-voltage devices, with exceptions outlined in this appendix. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HLC908JL3E/jk3e/jk1e technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 218 mc68HLC908JL3E/jk3e/jk1e motorola a.3 flash memory the flash memory can be read at minimum v dd of 2.2v. program or erase operations require a minimum v dd of 2.7v. a.4 low-voltage inhibit there is no low-voltage inhibit circuit. therefore, no low-voltage reset. the associated register bits are reserved bits. a.5 oscillator options only crystal oscillator or direct clock input is supported. a.6 electrical specifications electrical specifications for low-voltage devices are given in the following tables. a.6.1 functional operating range table a-1. operating range characteristic symbol value unit operating temperature range t a 0 to +85 c operating voltage range v dd 2.2 to 5.5 v operating voltage for flash memory program and erase operations v dd 2.7 to 5.5 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HLC908JL3E/jk3e/jk1e mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola mc68HLC908JL3E/jk3e/jk1e 219 a.6.2 dc electrical characteristics table a-2. dc electrical characteristics characteristic (1) notes: 1. v dd = 2.4 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ (2) 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ? 1.0ma) pta0 ? pta6, ptb0 ? ptb7, ptd0 ? ptd7 v oh v dd ? 0.4 ?? v output low voltage (i load = 0.8ma) pta6, ptb0 ? ptb7, ptd0, ptd1, ptd4, ptd5 v ol ?? 0.4 v output low voltage (i load = 15ma) ptd6, ptd7 v ol ?? 0.5 v input high voltage pta0 ? pta6, ptb0 ? ptb7, ptd0 ? ptd7, rst , irq1 , osc1 v ih 0.7 v dd ? v dd v input low voltage pta0 ? pta6, ptb0 ? ptb7, ptd0 ? ptd7, rst , irq1 , osc1 v il v ss ? 0.2 v dd v v dd supply current (v dd = 2.4v, f op = 2mhz) run (3) wait (4) stop (5) 0 c to 85 c 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source; all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly affects wait i dd . 5. stop i dd measured with osc1 grounded, no port pins sourcing current. lvi is disabled. i dd ? ? ? 2 1 1 3.5 1.5 3 ma ma a digital i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (6) 6. maximum is highest voltage that por is guaranteed. v por 0 ? 100 mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until min- imum v dd is reached. r por 0.02 ?? v/ms pullup resistors (8) ptd6, ptd7 rst , irq1 , pta0 ? pta6 8. r pu1 and r pu2 are measured at v dd = 5.0v r pu1 r pu2 1.8 16 3.3 26 4.8 36 k ? k ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HLC908JL3E/jk3e/jk1e technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 220 mc68HLC908JL3E/jk3e/jk1e motorola a.6.3 control timing a.6.4 oscillator characteristics table a-3. control timing characteristic (1) notes: 1. v dd = 2.2 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this infor- mation. f op ? 2mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 1.5 ? s table a-4. oscillator component specifications characteristic symbol min typ max unit crystal frequency, xtalclk f oscxclk ?? 8mhz external clock reference frequency (1) notes: 1. no more than 10% duty cycle deviation from 50% f oscxclk dc ? 8mhz crystal load capacitance (2) 2. consult crystal vendor data sheet c l ?? ? crystal fixed capacitance (2) c 1 ? 2 c l ? crystal tuning capacitance (2) c 2 ? 2 c l ? feedback bias resistor r b ? 10 m ? ? series resistor (2), (3) 3. not required for high frequency crystals r s ?? ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HLC908JL3E/jk3e/jk1e mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola mc68HLC908JL3E/jk3e/jk1e 221 a.6.5 adc characteristics table a-5. adc characteristics characteristic symbol min max unit comments supply voltage v ddad 2.2 (v dd min) 5.5 (v dd max) v input voltages v adin v ss v dd v resolution b ad 88bits absolute accuracy a ad 0.5 2 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v ss v dd v power-up time t adpu 14 ? t aic cycles conversion time t adc 14 15 t aic cycles sample time (1) notes: 1. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. t ads 5 ? t aic cycles zero input reading (2) 2. zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. z adi 00 01 hex v in = v ss full-scale reading (3) f adi fe ff hex v in = v dd input capacitance c adi ? (20) 8 pf not tested input leakage (3) port b/port d 3. the external system error caused by input leakage current is approximately equal to the product of r source and input current. ?? 1 a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HLC908JL3E/jk3e/jk1e technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 222 mc68HLC908JL3E/jk3e/jk1e motorola a.6.6 memory characteristics the flash memory can only be read at an operating voltage of 2.2 to 5.5v. program and erase are achieved at an operating voltage of 2.7 to 5.5v. the program and erase parameters in table a-6 are for v dd = 2.7 to 5.5v only. table a-6. memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v flash program bus clock frequency ? 1 ? mhz flash read bus clock frequency f read (1) 32k 8m hz flash page erase time t erase (2) 1 ? ms flash mass erase time t merase (3) 4 ? ms flash pgm/erase to hven set up time t nvs 10 ? s flash high-voltage hold time t nvh 5 ? s flash high-voltage hold time (mass erase) t nvhl 100 ? s flash program hold time t pgs 5 ? s flash program time t prog 30 40 s flash return to read time t rcv (4) 1 ? s flash cumulative program hv period t hv (5) ? 4ms flash row erase endurance (6) ? 10k ? cycles flash row program endurance (7) ? 10k ? cycles flash data retention time (8) ? 10 ? years notes: 1. f read is defined as the frequency range for which the flash memory can be read. 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 32) t hv max. 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. 8. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HLC908JL3E/jk3e/jk1e mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 technical data motorola mc68HLC908JL3E/jk3e/jk1e 223 a.7 mc order numbers table a-7 shows the ordering numbers for the low-voltage devices. table a-7. mc68HLC908JL3E/jk3e/jk1e order numbers mc order number oscillator type flash memory package mc68hlc98jl3eifa crystal oscillator 4096 bytes 48-pin lqfp mc68hlc98jl3eip mc68hlc98jl3eidw crystal oscillator 4096 bytes 28-pin package mc68hlc98jk3eip mc68hlc98jk3eidw crystal oscillator 4096 bytes 20-pin package mc68hlc98jk1eip mc68hlc98jk1eidw crystal oscillator 1536 bytes notes: i = 0 c to +85 c p = plastic dual in-line package (pdip) dw = small outline integrated circuit package (soic) fa = low-profile quad flat pack (lqfp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HLC908JL3E/jk3e/jk1e technical data mc68h(r)c908jl3e/jk3e/jk1e ? rev. 2.0 224 mc68HLC908JL3E/jk3e/jk1e motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd.; sps, technical information center, 3-20-1, minami-azabu minato-ku, tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? ty p i c a l s ? must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2002 mc68hc908jl3e/d rev. 2.0 1 2 / 2002 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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